2017-01-11 13:31:49 +00:00
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#ifndef PIN_SHIELD_8_H_
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#define PIN_SHIELD_8_H_
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// just provide macros for the 8-bit data bus
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// i.e. write_8(), read_8(), setWriteDir(), setReadDir()
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#define LPC810 810
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#define LPC812 812
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#define LPC1343 1343
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#define LPC1768 1768
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#define LPC2103 2103
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#define LPC2148 2148
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2018-07-17 09:54:14 +01:00
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#define ISTARGET_NUCLEO64 (0 \
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|| defined(TARGET_NUCLEO_F072RB) \
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|| defined(TARGET_NUCLEO_F103RB) \
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|| defined(TARGET_NUCLEO_F401RE) \
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|| defined(TARGET_NUCLEO_F411RE) \
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|| defined(TARGET_NUCLEO_F446RE) \
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|| defined(TARGET_NUCLEO_L433RC_P) \
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|| defined(TARGET_NUCLEO_L476RG) \
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)
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2018-12-13 10:52:31 +00:00
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#define ISTARGET_NUCLEO144 (0 \
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|| defined(TARGET_NUCLEO_F767ZI) \
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)
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2017-03-27 16:34:21 +01:00
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//#warning Using pin_SHIELD_8.h
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2017-01-11 13:31:49 +00:00
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#if 0
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2017-04-19 22:16:58 +01:00
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#elif defined(MY_BLUEPILL) // Uno Shield on BLUEPILL_ADAPTER
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#warning Uno Shield on MY_BLUEPILL_ADAPTER
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// configure macros for the data pins
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#define AMASK 0x060F
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#define BMASK 0x00C0
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#define write_8(d) { GPIOA->BSRR = AMASK << 16; GPIOB->BSRR = BMASK << 16; \
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GPIOA->BSRR = (((d) & 3) << 9) | (((d) & 0xF0) >> 4); \
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GPIOB->BSRR = (((d) & 0x0C) << 4); \
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}
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#define read_8() (((GPIOA->IDR & (3<<9)) >> 9) | ((GPIOA->IDR & (0x0F)) << 4) | ((GPIOB->IDR & (3<<6)) >> 4))
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#define GROUP_MODE(port, reg, mask, val) {port->reg = (port->reg & ~(mask)) | ((mask)&(val)); }
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#define GP_OUT(port, reg, mask) GROUP_MODE(port, reg, mask, 0x33333333)
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#define GP_INP(port, reg, mask) GROUP_MODE(port, reg, mask, 0x44444444)
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// PA10,PA9 PA3-PA0 PB7,PB6
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#define setWriteDir() {GP_OUT(GPIOA, CRH, 0xFF0); GP_OUT(GPIOA, CRL, 0xFFFF); GP_OUT(GPIOB, CRL, 0xFF000000); }
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#define setReadDir() {GP_INP(GPIOA, CRH, 0xFF0); GP_INP(GPIOA, CRL, 0xFFFF); GP_INP(GPIOB, CRL, 0xFF000000); }
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2017-03-27 16:34:21 +01:00
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#elif defined(BLUEPILL) // Uno Shield on BLUEPILL_ADAPTER
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2017-03-23 15:46:37 +00:00
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#warning Uno Shield on BLUEPILL_ADAPTER
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// configure macros for the data pins
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#define write_8(d) { GPIOA->BSRR = 0x00FF << 16; GPIOA->BSRR = (d) & 0xFF; }
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#define read_8() (GPIOA->IDR & 0xFF)
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#define GROUP_MODE(port, reg, mask, val) {port->reg = (port->reg & ~(mask)) | ((mask)&(val)); }
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#define GP_OUT(port, reg, mask) GROUP_MODE(port, reg, mask, 0x33333333)
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#define GP_INP(port, reg, mask) GROUP_MODE(port, reg, mask, 0x44444444)
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// PA7 ..PA0
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#define setWriteDir() {GP_OUT(GPIOA, CRL, 0xFFFFFFFF); }
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#define setReadDir() {GP_INP(GPIOA, CRL, 0xFFFFFFFF); }
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2017-03-27 16:34:21 +01:00
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#elif defined(ITEADMAPLE) // Uno Shield on MAPLE_REV3 board
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#warning Uno Shield on MAPLE_REV3 board
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#define REGS(x) x
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#define GROUP_MODE(port, reg, mask, val) {port->REGS(reg) = (port->REGS(reg) & ~(mask)) | ((mask)&(val)); }
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#define GP_OUT(port, reg, mask) GROUP_MODE(port, reg, mask, 0x33333333)
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#define GP_INP(port, reg, mask) GROUP_MODE(port, reg, mask, 0x44444444)
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2018-07-17 09:54:14 +01:00
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// configure macros for the data pins
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2017-03-27 16:34:21 +01:00
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#define write_8(d) { \
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GPIOA->REGS(BSRR) = 0x0703 << 16; \
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GPIOB->REGS(BSRR) = 0x00E0 << 16; \
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GPIOA->REGS(BSRR) = ( ((d) & (1<<0)) << 10) \
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| (((d) & (1<<2)) >> 2) \
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| (((d) & (1<<3)) >> 2) \
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| (((d) & (1<<6)) << 2) \
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| (((d) & (1<<7)) << 2); \
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GPIOB->REGS(BSRR) = ( ((d) & (1<<1)) << 6) \
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| (((d) & (1<<4)) << 1) \
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| (((d) & (1<<5)) << 1); \
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}
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#define read_8() ( ( ( (GPIOA->REGS(IDR) & (1<<10)) >> 10) \
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| ((GPIOB->REGS(IDR) & (1<<7)) >> 6) \
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| ((GPIOA->REGS(IDR) & (1<<0)) << 2) \
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| ((GPIOA->REGS(IDR) & (1<<1)) << 2) \
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| ((GPIOB->REGS(IDR) & (1<<5)) >> 1) \
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| ((GPIOB->REGS(IDR) & (1<<6)) >> 1) \
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| ((GPIOA->REGS(IDR) & (1<<8)) >> 2) \
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| ((GPIOA->REGS(IDR) & (1<<9)) >> 2)))
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// PA10,PA9,PA8 PA1,PA0 PB7,PB6,PB5
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#define setWriteDir() {GP_OUT(GPIOA, CRH, 0xFFF); GP_OUT(GPIOA, CRL, 0xFF); GP_OUT(GPIOB, CRL, 0xFFF00000); }
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#define setReadDir() {GP_INP(GPIOA, CRH, 0xFFF); GP_INP(GPIOA, CRL, 0xFF); GP_INP(GPIOB, CRL, 0xFFF00000); }
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2018-12-13 10:52:31 +00:00
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#elif defined(NUCLEO144) || ISTARGET_NUCLEO144
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#if __MBED__
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#warning MBED knows everything
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#elif defined(STM32F767xx)
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#include <STM32F7XX.h>
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#endif
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#define REGS(x) x
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// configure macros for the data pins
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#define DMASK ((1<<15)) //#1
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#define EMASK ((1<<13)|(1<<11)|(1<<9)) //#3, #5, #6
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#define FMASK ((1<<12)|(1<<15)|(1<<14)|(1<<13)) //#0, #2, #4, #7
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#define write_8(d) { \
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GPIOD->REGS(BSRR) = DMASK << 16; \
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GPIOE->REGS(BSRR) = EMASK << 16; \
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GPIOF->REGS(BSRR) = FMASK << 16; \
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GPIOD->REGS(BSRR) = ( ((d) & (1<<1)) << 14); \
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GPIOE->REGS(BSRR) = ( ((d) & (1<<3)) << 10) \
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| (((d) & (1<<5)) << 6) \
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| (((d) & (1<<6)) << 3); \
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GPIOF->REGS(BSRR) = ( ((d) & (1<<0)) << 12) \
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| (((d) & (1<<2)) << 13) \
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| (((d) & (1<<4)) << 10) \
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| (((d) & (1<<7)) << 6); \
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}
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#define read_8() ( ( ( (GPIOF->REGS(IDR) & (1<<12)) >> 12) \
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| ((GPIOD->REGS(IDR) & (1<<15)) >> 14) \
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| ((GPIOF->REGS(IDR) & (1<<15)) >> 13) \
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| ((GPIOE->REGS(IDR) & (1<<13)) >> 10) \
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| ((GPIOF->REGS(IDR) & (1<<14)) >> 10) \
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| ((GPIOE->REGS(IDR) & (1<<11)) >> 6) \
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| ((GPIOE->REGS(IDR) & (1<<9)) >> 3) \
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| ((GPIOF->REGS(IDR) & (1<<13)) >> 6)))
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// PD15 PE13,PE11,PE9 PF15,PF14,PF13,PF12
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#define setWriteDir() { setReadDir(); \
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GPIOD->MODER |= 0x40000000; GPIOE->MODER |= 0x04440000; GPIOF->MODER |= 0x55000000; }
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#define setReadDir() { GPIOD->MODER &= ~0xC0000000; GPIOE->MODER &= ~0x0CCC0000; GPIOF->MODER &= ~0xFF000000; }
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2018-07-17 09:54:14 +01:00
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#elif defined(NUCLEO) || ISTARGET_NUCLEO64
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2017-01-11 13:31:49 +00:00
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#if __MBED__
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#warning MBED knows everything
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#elif defined(STM32F072xB)
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#include <STM32F0XX.h>
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#elif defined(STM32F103xB)
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#if defined(__CC_ARM)
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#include <STM32F10X.h>
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#else
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#include <STM32F1XX.h>
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#endif
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2018-07-17 09:54:14 +01:00
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#elif defined(STM32L476xx) || defined(STM32L433xx)
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2017-01-11 13:31:49 +00:00
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#include <STM32L4XX.h>
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2018-05-14 23:02:20 +01:00
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#elif defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
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2017-01-11 13:31:49 +00:00
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#include <STM32F4XX.h>
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#endif
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// configure macros for the data pins. -00=10.06, -O1=7.85, -O1t=7.21, -O2=7.87, -O3=7.45, -O3t=7.03
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#define write_8(d) { \
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GPIOA->BSRR = 0x0700 << 16; \
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GPIOB->BSRR = 0x0438 << 16; \
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GPIOC->BSRR = 0x0080 << 16; \
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GPIOA->BSRR = (((d) & (1<<0)) << 9) \
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| (((d) & (1<<2)) << 8) \
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| (((d) & (1<<7)) << 1); \
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GPIOB->BSRR = (((d) & (1<<3)) << 0) \
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| (((d) & (1<<4)) << 1) \
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| (((d) & (1<<5)) >> 1) \
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| (((d) & (1<<6)) << 4); \
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GPIOC->BSRR = (((d) & (1<<1)) << 6); \
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}
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#define read_8() ( (((GPIOA->IDR & (1<<9)) >> 9) \
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| ((GPIOC->IDR & (1<<7)) >> 6) \
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| ((GPIOA->IDR & (1<<10)) >> 8) \
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| ((GPIOB->IDR & (1<<3)) >> 0) \
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| ((GPIOB->IDR & (1<<5)) >> 1) \
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| ((GPIOB->IDR & (1<<4)) << 1) \
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| ((GPIOB->IDR & (1<<10)) >> 4) \
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| ((GPIOA->IDR & (1<<8)) >> 1)))
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// be wise to clear both MODER bits properly.
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#if defined(STM32F103xB)
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#define GROUP_MODE(port, reg, mask, val) {port->reg = (port->reg & ~(mask)) | ((mask)&(val)); }
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#define GP_OUT(port, reg, mask) GROUP_MODE(port, reg, mask, 0x33333333)
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#define GP_INP(port, reg, mask) GROUP_MODE(port, reg, mask, 0x44444444)
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// PA10,PA9,PA8 PB10 PB5,PB4,PB3 PC7
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#define setWriteDir() {GP_OUT(GPIOA, CRH, 0xFFF); GP_OUT(GPIOB, CRH, 0xF00); GP_OUT(GPIOB, CRL, 0xFFF000); GP_OUT(GPIOC, CRL, 0xF0000000); }
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#define setReadDir() {GP_INP(GPIOA, CRH, 0xFFF); GP_INP(GPIOB, CRH, 0xF00); GP_INP(GPIOB, CRL, 0xFFF000); GP_INP(GPIOC, CRL, 0xF0000000); }
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#else
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#define setWriteDir() { setReadDir(); \
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GPIOA->MODER |= 0x150000; GPIOB->MODER |= 0x100540; GPIOC->MODER |= 0x4000; }
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#define setReadDir() { GPIOA->MODER &= ~0x3F0000; GPIOB->MODER &= ~0x300FC0; GPIOC->MODER &= ~0xC000; }
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#endif
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2017-02-18 21:38:37 +00:00
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2017-01-11 13:31:49 +00:00
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#elif __TARGET_PROCESSOR == LPC1768
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#include <LPC17xx.h>
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// configure macros for the data pins
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#define write_8(d) { \
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LPC_GPIO0->FIOPIN = (LPC_GPIO0->FIOPIN & ~0x01878003) \
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| (((d) & (1<<0)) << 1) \
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| (((d) & (1<<1)) >> 1) \
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| (((d) & (1<<2)) << 22) \
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| (((d) & (1<<3)) << 20) \
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| (((d) & (1<<4)) << 12) \
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| (((d) & (1<<5)) << 10) \
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| (((d) & (1<<6)) << 11) \
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| (((d) & (1<<7)) << 11); \
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}
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#define read_8() ( (((LPC_GPIO0->FIOPIN & (1<<1)) >> 1) \
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| ((LPC_GPIO0->FIOPIN & (1<<0)) << 1) \
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| ((LPC_GPIO0->FIOPIN & (1<<24)) >> 22) \
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| ((LPC_GPIO0->FIOPIN & (1<<23)) >> 20) \
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| ((LPC_GPIO0->FIOPIN & (1<<16)) >> 12) \
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| ((LPC_GPIO0->FIOPIN & (1<<15)) >> 10) \
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| ((LPC_GPIO0->FIOPIN & (1<<17)) >> 11) \
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| ((LPC_GPIO0->FIOPIN & (1<<18)) >> 11)))
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#define setWriteDir() {LPC_GPIO0->FIODIR |= 0x01878003; }
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#define setReadDir() {LPC_GPIO0->FIODIR &= ~0x01878003; }
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#elif defined(MKL25Z4) || defined(TARGET_KL25Z)
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#include <MKL25Z4.h>
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// configure macros for the data pins
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#if 1
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#define AMASK ((1<<13)|(1<<12)|(1<<5)|(1<<4))
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#define CMASK ((1<<9)|(1<<8))
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#define DMASK ((1<<5)|(1<<4))
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#define write_8(d) { \
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PTA->PCOR = AMASK; PTC->PCOR = CMASK; PTD->PCOR = DMASK; \
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PTA->PSOR = (((d) & (1<<0)) << 13) \
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| (((d) & (1<<3)) << 9) \
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| (((d) & (1<<4)) >> 0) \
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| (((d) & (1<<5)) >> 0); \
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PTC->PSOR = (((d) & (1<<6)) << 2) \
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| (((d) & (1<<7)) << 2); \
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PTD->PSOR = (((d) & (1<<1)) << 4) \
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| (((d) & (1<<2)) << 2); \
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}
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#define read_8() ( (((PTA->PDIR & (1<<13)) >> 13) \
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| ((PTA->PDIR & (1<<12)) >> 9) \
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| ((PTA->PDIR & (3<<4)) >> 0) \
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| ((PTC->PDIR & (3<<8)) >> 2) \
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| ((PTD->PDIR & (1<<4)) >> 2) \
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| ((PTD->PDIR & (1<<5)) >> 4)))
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#define setWriteDir() {PTA->PDDR |= AMASK;PTC->PDDR |= CMASK;PTD->PDDR |= DMASK; }
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#define setReadDir() {PTA->PDDR &= ~AMASK;PTC->PDDR &= ~CMASK;PTD->PDDR &= ~DMASK; }
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#else
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#define write_8(d) { \
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PTA->PDOR = (PTA->PDOR & ~0x3030) \
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| (((d) & (1<<0)) << 13) \
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| (((d) & (1<<3)) << 9) \
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| (((d) & (3<<4)) << 0); \
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PTC->PDOR = (PTC->PDOR & ~0x0300) \
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| (((d) & (3<<6)) << 2); \
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PTD->PDOR = (PTD->PDOR & ~0x0030) \
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| (((d) & (1<<1)) << 4) \
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| (((d) & (1<<2)) << 2); \
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}
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#define read_8() ( (((PTA->PDIR & (1<<13)) >> 13) \
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| ((PTA->PDIR & (1<<12)) >> 9) \
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| ((PTA->PDIR & (3<<4)) >> 0) \
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| ((PTC->PDIR & (3<<8)) >> 2) \
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| ((PTD->PDIR & (1<<4)) >> 2) \
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| ((PTD->PDIR & (1<<5)) >> 4)))
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#define setWriteDir() {PTA->PDDR |= 0x3030;PTC->PDDR |= 0x0300;PTD->PDDR |= 0x0030; }
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#define setReadDir() {PTA->PDDR &= ~0x3030;PTC->PDDR &= ~0x0300;PTD->PDDR &= ~0x0030; }
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#endif
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2017-01-31 09:39:53 +00:00
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#elif defined(MKL26Z4)
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#include <MKL26Z4.h>
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// configure macros for the data pins
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#define AMASK ((1<<13)|(1<<12)|(1<<5)|(1<<4))
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#define CMASK ((1<<9)|(1<<8))
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#define DMASK ((1<<3)|(1<<2)) //PTD5, PTD4 on KL25Z
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#define write_8(d) { \
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PTA->PCOR = AMASK; PTC->PCOR = CMASK; PTD->PCOR = DMASK; \
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PTA->PSOR = (((d) & (1<<0)) << 13) \
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| (((d) & (1<<3)) << 9) \
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| (((d) & (1<<4)) >> 0) \
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| (((d) & (1<<5)) >> 0); \
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PTC->PSOR = (((d) & (1<<6)) << 2) \
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| (((d) & (1<<7)) << 2); \
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PTD->PSOR = (((d) & (1<<1)) << 1) \
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| (((d) & (1<<2)) << 1); \
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}
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#define read_8() ( (((PTA->PDIR & (1<<13)) >> 13) \
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| ((PTA->PDIR & (1<<12)) >> 9) \
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| ((PTA->PDIR & (3<<4)) >> 0) \
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| ((PTC->PDIR & (3<<8)) >> 2) \
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| ((PTD->PDIR & (1<<3)) >> 1) \
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| ((PTD->PDIR & (1<<2)) >> 1)))
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#define setWriteDir() {PTA->PDDR |= AMASK;PTC->PDDR |= CMASK;PTD->PDDR |= DMASK; }
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#define setReadDir() {PTA->PDDR &= ~AMASK;PTC->PDDR &= ~CMASK;PTD->PDDR &= ~DMASK; }
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2017-01-11 13:31:49 +00:00
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#elif defined(MKL05Z4) || defined(TARGET_KL05Z)
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#include <MKL05Z4.h>
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// configure macros for the data pins
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#define write_8(d) { \
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PTA->PDOR = (PTA->PDOR & ~0x1C00) \
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| (((d) & (1<<2)) << 9) \
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| (((d) & (1<<4)) << 6) \
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| (((d) & (1<<5)) << 7); \
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PTB->PDOR = (PTB->PDOR & ~0x0CE0) \
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| (((d) & (3<<0)) << 10) \
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| (((d) & (1<<3)) << 2) \
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| (((d) & (3<<6)) << 0); \
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}
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#define read_8() ( (((PTA->PDIR & (1<<11)) >> 9) \
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| ((PTA->PDIR & (1<<10)) >> 6) \
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| ((PTA->PDIR & (1<<12)) >> 7) \
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| ((PTB->PDIR & (3<<10)) >> 10) \
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| ((PTB->PDIR & (1<<5)) >> 2) \
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| ((PTB->PDIR & (3<<6)) >> 0)))
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#define setWriteDir() { PTA->PDDR |= 0x1C00; PTB->PDDR |= 0x0CE0; }
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#define setReadDir() { PTA->PDDR &= ~0x1C00; PTB->PDDR &= ~0x0CE0; }
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2017-02-18 21:38:37 +00:00
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#elif (defined(MK20D7) && defined(TEENSY)) || defined(TARGET_TEENSY3_1)
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#if __MBED__
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#warning MBED knows everything
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#else
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2017-01-11 13:31:49 +00:00
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#include <MK20D5.h>
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2017-02-18 21:38:37 +00:00
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#endif
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2017-01-11 13:31:49 +00:00
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// configure macros for the data pins
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#define AMASK ((1<<12)|(1<<13))
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#define CMASK ((1<<3))
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#define DMASK ((1<<0)|(1<<2)|(1<<3)|(1<<4)|(1<<7))
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#define write_8(d) { \
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PTA->PCOR = AMASK; PTC->PCOR = CMASK; PTD->PCOR = DMASK; \
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PTA->PSOR = (((d) & (1<<3)) << 9) \
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| (((d) & (1<<4)) << 9); \
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PTC->PSOR = (((d) & (1<<1)) << 2); \
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PTD->PSOR = (((d) & (1<<0)) << 3) \
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| (((d) & (1<<2)) >> 2) \
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| (((d) & (1<<5)) << 2) \
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| (((d) & (1<<6)) >> 2) \
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| (((d) & (1<<7)) >> 5); \
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}
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#define read_8() ( (((PTD->PDIR & (1<<3)) >> 3) \
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| ((PTC->PDIR & (1<<3)) >> 2) \
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| ((PTD->PDIR & (1<<0)) << 2) \
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| ((PTA->PDIR & (1<<12)) >> 9) \
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| ((PTA->PDIR & (1<<13)) >> 9) \
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| ((PTD->PDIR & (1<<7)) >> 2) \
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| ((PTD->PDIR & (1<<4)) << 2) \
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| ((PTD->PDIR & (1<<2)) << 5)))
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#define setWriteDir() {PTA->PDDR |= AMASK;PTC->PDDR |= CMASK;PTD->PDDR |= DMASK; }
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#define setReadDir() {PTA->PDDR &= ~AMASK;PTC->PDDR &= ~CMASK;PTD->PDDR &= ~DMASK; }
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#elif defined(MK20D5) || defined(TARGET_K20D50M)
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#include <MK20D5.h>
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// configure macros for the data pins
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#define AMASK ((1<<12)|(1<<5)|(1<<2)|(1<<1))
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#define CMASK ((1<<8)|(1<<4)|(1<<3))
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#define DMASK ((1<<4))
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#define write_8(d) { \
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PTA->PCOR = AMASK; PTC->PCOR = CMASK; PTD->PCOR = DMASK; \
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PTA->PSOR = (((d) & (1<<0)) << 12) \
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| (((d) & (1<<1)) << 1) \
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| (((d) & (1<<2)) << 3) \
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| (((d) & (1<<5)) >> 4); \
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PTC->PSOR = (((d) & (1<<4)) << 4) \
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| (((d) & (3<<6)) >> 3); \
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PTD->PSOR = (((d) & (1<<3)) << 1); \
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}
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#define read_8() ( (((PTA->PDIR & (1<<5)) >> 3) \
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| ((PTA->PDIR & (1<<1)) << 4) \
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| ((PTA->PDIR & (1<<12)) >> 12) \
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| ((PTA->PDIR & (1<<2)) >> 1) \
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| ((PTC->PDIR & (1<<8)) >> 4) \
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| ((PTC->PDIR & (3<<3)) << 3) \
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| ((PTD->PDIR & (1<<4)) >> 1)))
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#define setWriteDir() {PTA->PDDR |= AMASK;PTC->PDDR |= CMASK;PTD->PDDR |= DMASK; }
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#define setReadDir() {PTA->PDDR &= ~AMASK;PTC->PDDR &= ~CMASK;PTD->PDDR &= ~DMASK; }
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#elif defined(ZERO)
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#include <samd21.h>
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#ifndef PORTA
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#define PORTA PORT->Group[0]
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#define PORTB PORT->Group[1]
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#endif
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// configure macros for the data pins
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#if defined(D21_XPRO)
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#define AMASK 0x00220000
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#define BMASK 0x0000C0E4
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#define write_8(d) { \
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PORTA.OUT.reg = (PORTA.OUT.reg & ~AMASK) \
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| (((d) & (1<<5)) << 16) \
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| (((d) & (1<<7)) << 10); \
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PORTB.OUT.reg = (PORTB.OUT.reg & ~BMASK) \
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| (((d) & (3<<0)) << 6) \
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| (((d) & (1<<2)) << 12) \
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| (((d) & (1<<3)) >> 1) \
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| (((d) & (1<<4)) << 1) \
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| (((d) & (1<<6)) << 9); \
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}
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#define read_8() ( (((PORTA.IN.reg & (1<<21)) >> 16) \
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| ((PORTA.IN.reg & (1<<17)) >> 10) \
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| ((PORTB.IN.reg & (3<<6)) >> 6) \
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| ((PORTB.IN.reg & (1<<14)) >> 12) \
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| ((PORTB.IN.reg & (1<<2)) << 1) \
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| ((PORTB.IN.reg & (1<<5)) >> 1) \
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| ((PORTB.IN.reg & (1<<15)) >> 9)))
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#define setWriteDir() { \
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PORTA.DIRSET.reg = AMASK; \
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PORTB.DIRSET.reg = BMASK; \
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PORTA.WRCONFIG.reg = (AMASK>>16) | (0<<22) | (0<<28) | (1<<30) | (1<<31); \
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PORTB.WRCONFIG.reg = (BMASK & 0xFFFF) | (0<<22) | (0<<28) | (1<<30); \
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}
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#define setReadDir() { \
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PORTA.DIRCLR.reg = AMASK; \
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PORTB.DIRCLR.reg = BMASK; \
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PORTA.WRCONFIG.reg = (AMASK>>16) | (1<<17) | (0<<28) | (1<<30) | (1<<31); \
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PORTB.WRCONFIG.reg = (BMASK & 0xFFFF) | (1<<17) | (0<<28) | (1<<30); \
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}
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#else
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#define DMASK 0x0030C3C0
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|
#define write_8(x) {PORTA.OUTCLR.reg = (DMASK); \
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PORTA.OUTSET.reg = (((x) & 0x0F) << 6) \
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| (((x) & 0x30) << 10) \
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| (((x) & 0xC0)<<14); }
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#define read_8() (((PORTA.IN.reg >> 6) & 0x0F) \
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|
|
|
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| ((PORTA.IN.reg >> 10) & 0x30) \
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|
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| ((PORTA.IN.reg >> 14) & 0xC0))
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|
|
#define setWriteDir() { PORTA.DIRSET.reg = DMASK; \
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|
|
|
|
PORTA.WRCONFIG.reg = (DMASK & 0xFFFF) | (0<<22) | (1<<28) | (1<<30); \
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PORTA.WRCONFIG.reg = (DMASK>>16) | (0<<22) | (1<<28) | (1<<30) | (1<<31); \
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}
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|
|
#define setReadDir() { PORTA.DIRCLR.reg = DMASK; \
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|
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|
|
PORTA.WRCONFIG.reg = (DMASK & 0xFFFF) | (1<<17) | (1<<28) | (1<<30); \
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|
PORTA.WRCONFIG.reg = (DMASK>>16) | (1<<17) | (1<<28) | (1<<30) | (1<<31); \
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}
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|
#endif
|
2019-11-19 17:33:34 +00:00
|
|
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|
|
//####################################### DUE ############################
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|
|
#elif defined(__SAM3X8E__) //regular UNO shield on DUE
|
|
|
|
|
|
// configure macros for data bus
|
|
|
|
|
|
#define BMASK (1<<25)
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|
|
#define CMASK (0xBF << 21)
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|
|
#define write_8(x) { PIOB->PIO_CODR = BMASK; PIOC->PIO_CODR = CMASK; \
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|
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|
|
PIOB->PIO_SODR = (((x) & (1<<2)) << 23); \
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|
|
PIOC->PIO_SODR = (((x) & (1<<0)) << 22) \
|
|
|
|
|
|
| (((x) & (1<<1)) << 20) \
|
|
|
|
|
|
| (((x) & (1<<3)) << 25) \
|
|
|
|
|
|
| (((x) & (1<<4)) << 22) \
|
|
|
|
|
|
| (((x) & (1<<5)) << 20) \
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| (((x) & (1<<6)) << 18) \
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| (((x) & (1<<7)) << 16); \
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}
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#define read_8() ( ((PIOC->PIO_PDSR & (1<<22)) >> 22)\
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| ((PIOC->PIO_PDSR & (1<<21)) >> 20)\
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| ((PIOB->PIO_PDSR & (1<<25)) >> 23)\
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| ((PIOC->PIO_PDSR & (1<<28)) >> 25)\
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| ((PIOC->PIO_PDSR & (1<<26)) >> 22)\
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| ((PIOC->PIO_PDSR & (1<<25)) >> 20)\
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| ((PIOC->PIO_PDSR & (1<<24)) >> 18)\
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| ((PIOC->PIO_PDSR & (1<<23)) >> 16)\
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)
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#define setWriteDir() { PIOB->PIO_OER = BMASK; PIOC->PIO_OER = CMASK; }
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#define setReadDir() { \
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PMC->PMC_PCER0 = (1 << ID_PIOB)|(1 << ID_PIOC);\
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PIOB->PIO_ODR = BMASK; PIOC->PIO_ODR = CMASK;\
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}
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2017-01-11 13:31:49 +00:00
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#else
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#error MCU unselected
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#endif // MCUs
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#endif //PIN_SHIELD_8_H
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