mirror of
https://github.com/YuzuZensai/MCUFRIEND_kbv.git
synced 2026-01-30 12:22:43 +00:00
tidy up XMEGA boards
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prenticedavid
@@ -87,102 +87,87 @@ ST7796S tWC = 66ns tWRH = 15ns tRCFM = 450ns tRC = 160ns
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#define PIN_HIGH(port, pin) (port)->gpio_set = (1<<(pin))
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#define PIN_OUTPUT(port, pin) (port)->gpio_oe_set = (1<<(pin))
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#elif defined(__AVR_ATxmega128A1__) // Xplained or MIKROE
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#if defined(USE_MIKROELEKTRONIKA) // HX8347-D 16.2ns@62MHz 20.9ns@48MHz
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//################################### XMEGA BOARDS ##############################
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#elif defined(__AVR_ATxmega128A1__)||defined(__AVR_ATxmega128A4U__)||defined(__AVR_ATxmega32A4U__)||defined(__AVR_ATxmega32E5__)
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#if defined(__AVR_ATxmega128A1__) && defined(USE_CVSTK600)
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#warning Home made shield with Xplained A1: CTL=J3 (PD), DATA=J2 (PA)
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#define VPMAP10 0x10 // VPORT0=A, 1=B, 2=C, 3=D
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#define VPMAP32 0x32 // VPORT0=A, 1=B, 2=C, 3=D
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#define DATPORT VPORT0 //PORTA
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#define CTLPORT VPORT3 //PORTD
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#define RD_PORT CTLPORT //PD2. use individual jumper cables
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#define RD_PIN 2
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#define WR_PORT CTLPORT
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#define WR_PIN 3
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#define CD_PORT CTLPORT
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#define CD_PIN 1
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#define CS_PORT CTLPORT
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#define CS_PIN 0
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#define RESET_PORT CTLPORT
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#define RESET_PIN 4
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#elif defined(__AVR_ATxmega128A1__) && defined(USE_MIKROELEKTRONIKA) // HX8347-D 16.2ns@62MHz 20.9ns@48MHz
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#if F_CPU > 46000000
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#error MIKROELEKTRONIKA must be less than 48MHz
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#else
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#warning MIKROELEKTRONIKA DEV BOARD (48MHz max)
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#endif
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#define WRITE_DELAY { }
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#define READ_DELAY { RD_ACTIVE4; }
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#define VPMAP10 0x58 // VPORT0=J, 1=F, 2=K, 3=D
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#define VPMAP32 0x39 // VPORT0=J, 1=F, 2=K, 3=D
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#define RD_PORT VPORT0 //PJ2.
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#define DATPORT VPORT2 //PORTK
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#define CTLPORT VPORT0 //PORTJ
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#define RD_PORT CTLPORT //PJ2.
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#define RD_PIN 2
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#define WR_PORT VPORT0
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#define WR_PORT CTLPORT
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#define WR_PIN 3
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#define CD_PORT VPORT0
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#define CD_PORT CTLPORT
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#define CD_PIN 4
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#define CS_PORT VPORT0
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#define CS_PORT CTLPORT
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#define CS_PIN 5
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#define RESET_PORT VPORT0 //PJ1
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#define RESET_PORT CTLPORT //PJ1
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#define RESET_PIN 1
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#else
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#warning Home made shield with Xplained CTL=J1 (PC), DATA=J4 (PF)
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#define WRITE_DELAY { }
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#define READ_DELAY { RD_ACTIVE4; }
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#define VPMAP10 0x15 // VPORT0=F, 1=B, 2=C, 3=D
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#define VPMAP32 0x32 // VPORT0=F, 1=B, 2=C, 3=D
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#define RD_PORT VPORT0 //PF0.
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#elif defined(__AVR_ATxmega128A1__)
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#warning Home made shield with Xplained A1 CTL=J4 (PC), DATA=J2 (PA)
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#define VPMAP10 0x50 // VPORT0=A, 1=F, 2=C, 3=D
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#define VPMAP32 0x32 // VPORT0=A, 1=F, 2=C, 3=D
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#define DATPORT VPORT0 //PORTA
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#define CTLPORT VPORT2 //PORTC
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#define RD_PORT CTLPORT //PC0.
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#define RD_PIN 0
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#define WR_PORT VPORT0
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#define WR_PORT CTLPORT
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#define WR_PIN 1
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#define CD_PORT VPORT0
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#define CD_PORT CTLPORT
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#define CD_PIN 2
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#define CS_PORT VPORT0
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#define CS_PORT CTLPORT
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#define CS_PIN 3
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#define RESET_PORT VPORT0 //PK4
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#define RESET_PORT CTLPORT //PC4
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#define RESET_PIN 4
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#endif
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// VPORTs are very fast. CBI, SBI are only one cycle. Hence all those RD_ACTIVEs
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// ILI9320 data sheet says tDDR=100ns. We need 218ns to read REGs correctly.
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#define write_8(x) { VPORT2.OUT = x; }
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#define read_8() ( VPORT2.IN )
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#define setWriteDir() { PORTCFG.VPCTRLA=VPMAP10; PORTCFG.VPCTRLB=VPMAP32; VPORT2.DIR = 0xFF; }
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#define setReadDir() { VPORT2.DIR = 0x00; }
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#define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; }
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#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
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//#define READ_8(dst) { RD_STROBE; RD_ACTIVE2; RD_ACTIVE; dst = read_8(); RD_IDLE; }
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#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; }
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#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
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#define PIN_LOW(p, b) (p).OUT &= ~(1<<(b))
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#define PIN_HIGH(p, b) (p).OUT |= (1<<(b))
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#define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b))
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#elif defined(__AVR_ATxmega32A4U__) || defined(__AVR_ATxmega128A4U__) // Home made shield with Batsocks module
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#warning Home made shield with Batsocks module
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#define RD_PORT VPORT1 //PB0. VPORT0=A, 1=B, 2=C, 3=D
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#define VPMAP10 0x10 // VPORT0=A, 1=B, 2=C, 3=D
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#define VPMAP32 0x32 // VPORT0=A, 1=B, 2=C, 3=D
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#define DATPORT VPORT2 //PORTC
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#define CTLPORT VPORT1 //PORTB
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#define RD_PORT CTLPORT //PB0.
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#define RD_PIN 0
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#define WR_PORT VPORT1
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#define WR_PORT CTLPORT
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#define WR_PIN 1
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#define CD_PORT VPORT1
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#define CD_PORT CTLPORT
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#define CD_PIN 2
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#define CS_PORT VPORT1
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#define CS_PORT CTLPORT
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#define CS_PIN 3
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#define RESET_PORT PORTE
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#define RESET_PIN 0
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// VPORTs are very fast. CBI, SBI are only one cycle. Hence all those RD_ACTIVEs
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// ILI9320 data sheet says tDDR=100ns. We need 218ns to read REGs correctly.
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// S6D0154 data sheet says tDDR=250ns. We need ~500ns to read REGs correctly.
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// ST7789 data sheet says tRC=450ns. We need ~167ns to read REGs correctly. (10 cycles @ 60MHz )
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// ST7789 says tRC=160ns for ID and tRC=450ns for Frame Memory
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// ILI9341 says tRC=160ns for ID and tRC=450ns for Frame Memory. They are FASTER
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#define WRITE_DELAY { }
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#define READ_DELAY { RD_ACTIVE4; }
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#define write_8(x) { VPORT2.OUT = x; }
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#define read_8() ( VPORT2.IN )
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#define setWriteDir() { PORTCFG.VPCTRLA=0x10; PORTCFG.VPCTRLB=0x32; VPORT2.DIR = 0xFF; }
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#define setReadDir() { VPORT2.DIR = 0x00; }
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#define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; }
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#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
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#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; }
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#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
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#define PIN_LOW(p, b) (p).OUT &= ~(1<<(b))
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#define PIN_HIGH(p, b) (p).OUT |= (1<<(b))
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#define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b))
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#elif defined(__AVR_ATxmega32E5__) // Xplained E5 F_CPU <= 46MHz
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#warning Home made shield with Xplained E5: CTL=J2 (PD), DATA=J0 (PA)
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#define CTLPORT VPORT2 //PORTD on J2
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#define DATPORT VPORT0 //PORTA on J3, SW103=hdr
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#define WRITE_DELAY { }
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#define READ_DELAY { RD_ACTIVE4; }
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#define RD_PORT CTLPORT
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#warning Home made shield with Xplained E5: CTL=J4 (PD), DATA=J2 (PA)
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//no VPMAPxx on 32E5. Fixed VPORT0=A, 1=C, 2=D, 3=R
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#define CTLPORT VPORT2 //PORTD on J4
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#define DATPORT VPORT0 //PORTA on J2, SW103=hdr
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#define RD_PORT CTLPORT //PD0.
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#define RD_PIN 0
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#define WR_PORT CTLPORT
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#define WR_PIN 1
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@@ -193,11 +178,25 @@ ST7796S tWC = 66ns tWRH = 15ns tRCFM = 450ns tRC = 160ns
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#define RESET_PORT CTLPORT //10k p.u. to 3V3
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#define RESET_PIN 4
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#endif //VPORT and pin mapping
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#if defined(VPMAP10)
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#define MAP_VPORTS() { PORTCFG.VPCTRLA=VPMAP10; PORTCFG.VPCTRLB=VPMAP32; }
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#else
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#define MAP_VPORTS()
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#endif
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// VPORTs are very fast. CBI, SBI are only one cycle. Hence all those RD_ACTIVEs
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// ILI9320 data sheet says tDDR=100ns. We need 218ns to read REGs correctly.
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// S6D0154 data sheet says tDDR=250ns. We need ~500ns to read REGs correctly.
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// ST7789 data sheet says tRC=450ns. We need ~167ns to read REGs correctly. (10 cycles @ 60MHz )
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// ST7789 says tRC=160ns for ID and tRC=450ns for Frame Memory
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// ILI9341 says tRC=160ns for ID and tRC=450ns for Frame Memory. They are FASTER
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#define WRITE_DELAY { }
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#define READ_DELAY { RD_ACTIVE4; }
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#define write_8(x) { DATPORT.OUT = x; }
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#define read_8() ( DATPORT.IN )
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#define setWriteDir() { DATPORT.DIR = 0xFF; }
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#define setWriteDir() { MAP_VPORTS(); DATPORT.DIR = 0xFF; }
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#define setReadDir() { DATPORT.DIR = 0x00; }
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#define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; }
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#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
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