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Merge pull request #46 from prenticedavid/temp_nucleo

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Temp nucleo
This commit is contained in:
prenticedavid
2018-04-29 14:17:33 +01:00
committed by GitHub
parent 22dfd1833c 4632c28704
commit 15b0532167
4 changed files with 67 additions and 29 deletions
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3
UTFTGLUE.h
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@@ -19,7 +19,8 @@
#include <MCUFRIEND_kbv.h>
#include <Adafruit_GFX.h>
#if !defined(AVR)
//#if !defined(AVR) && !defined(ESP32)
#if defined(__arm)
#include <avr/dtostrf.h>
#endif

27
utility/mcufriend_keil.h
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@@ -39,23 +39,26 @@
// General macros. IOCLR registers are 1 cycle when optimised.
#define WR_STROBE { WR_ACTIVE; WR_IDLE; } //PWLW=TWRL=50ns
#define RD_STROBE RD_IDLE, RD_ACTIVE, RD_ACTIVE, RD_ACTIVE //PWLR=TRDL=150ns
#if defined(TEENSY) || defined(__ARM_ARCH_7EM__) // || defined(STM32L476xx)
#define write8(d) { write_8(d); WR_ACTIVE; WR_ACTIVE; WR_STROBE; WR_IDLE; } // STROBEs are defined later
// read 250ns after RD_ACTIVE goes low
#define read8() ( RD_STROBE, RD_ACTIVE, RD_ACTIVE, RD_ACTIVE, RD_ACTIVE, RD_ACTIVE, RD_ACTIVE, read_8() )
#else
#define write8(d) { write_8(d); WR_STROBE; } // STROBEs are defined later
// read 250ns after RD_ACTIVE goes low
#define read8() ( RD_STROBE, read_8() )
#if defined(TEENSY) || defined(__ARM_ARCH_7EM__) // -O2: F411@100MHz = 1.44s
#define WRITE_DELAY { WR_ACTIVE; WR_ACTIVE; WR_ACTIVE; }
#define READ_DELAY { RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; }
#elif defined(__ARM_ARCH_7M__) // -O2: F103@72MHz = 2.68s
#define WRITE_DELAY { }
#define READ_DELAY { RD_ACTIVE; }
#elif defined(__ARM_ARCH_6M__) // -O2: F072@48MHz = 5.03s
#define WRITE_DELAY { }
#define READ_DELAY { }
#endif
#define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; }
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
#define READ_8(dst) { dst = read8(); RD_IDLE; }
#define READ_16(dst) { dst = read8(); dst = (dst<<8) | read8(); RD_IDLE; }
#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; } // read 250ns after RD_ACTIVE goes low
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
#define CTL_INIT() { RD_OUTPUT; WR_OUTPUT; CD_OUTPUT; CS_OUTPUT; RESET_OUTPUT; }
#define WriteCmd(x) { CD_COMMAND; write16(x); }
#define WriteData(x) { CD_DATA; write16(x); }
#define WriteCmd(x) { CD_COMMAND; write16(x); CD_DATA; }
#define WriteData(x) { write16(x); }
#endif //!USE_SERIAL
#endif //MCUFRIEND_KEIL_H_

63
utility/mcufriend_shield.h
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@@ -336,15 +336,17 @@ void write_8(uint8_t x)
//####################################### STM32 ############################
// NUCLEO: ARDUINO_NUCLEO_xxxx from ST Core or ARDUINO_STM_NUCLEO_F103RB from MapleCore
// BLUEPILL: ARDUINO_NUCLEO_F103C8 from ST Core or ARDUINO_GENERIC_STM32F103C from MapleCore
// BLUEPILL: ARDUINO_NUCLEO_F103C8 / ARDUINO_BLUEPILL_F103C8 from ST Core or ARDUINO_GENERIC_STM32F103C from MapleCore
// MAPLE_REV3: n/a from ST Core or ARDUINO_MAPLE_REV3 from MapleCore
// ST Core: ARDUINO_ARCH_STM32
// MapleCore: __STM32F1__
#elif defined(__STM32F1__) || defined(ARDUINO_ARCH_STM32) //MapleCore or ST Core
#define IS_NUCLEO ( defined(ARDUINO_STM_NUCLEO_F103RB) || defined(ARDUINO_NUCLEO_F103RB) \
|| defined(ARDUINO_NUCLEO_L476RG) \
#define IS_NUCLEO64 ( defined(ARDUINO_STM_NUCLEO_F103RB) \
|| defined(ARDUINO_NUCLEO_F030R8) || defined(ARDUINO_NUCLEO_F091RC) \
|| defined(ARDUINO_NUCLEO_F103RB) || defined(ARDUINO_NUCLEO_F303RE) \
|| defined(ARDUINO_NUCLEO_F401RE) || defined(ARDUINO_NUCLEO_F411RE) \
)
|| defined(ARDUINO_NUCLEO_L053R8) || defined(ARDUINO_NUCLEO_L476RG) \
)
// F1xx, F4xx, L4xx have different registers and styles. General Macros
#if defined(__STM32F1__) //weird Maple Core
#define REGS(x) regs->x
@@ -357,8 +359,9 @@ void write_8(uint8_t x)
#define GROUP_MODE(port, reg, mask, val) {port->REGS(reg) = (port->REGS(reg) & ~(mask)) | ((mask)&(val)); }
// Family specific Macros. F103 needs ST and Maple compatibility
// note that ILI9320 class of controller has much slower Read cycles
#if 0
#elif defined(__STM32F1__) || defined(ARDUINO_NUCLEO_F103C8) || defined(ARDUINO_NUCLEO_F103RB)
#elif defined(__STM32F1__) || defined(ARDUINO_NUCLEO_F103C8) || defined(ARDUINO_BLUEPILL_F103C8) || defined(ARDUINO_NUCLEO_F103RB)
#define WRITE_DELAY { }
#define READ_DELAY { RD_ACTIVE; }
#if defined(__STM32F1__) //MapleCore crts.o does RCC. not understand regular syntax anyway
@@ -379,28 +382,58 @@ void write_8(uint8_t x)
}
// should be easy to add F030, F091, F303, L053, ...
#elif defined(STM32F030x8)
#define WRITE_DELAY { }
#define READ_DELAY { RD_ACTIVE; }
#define GPIO_INIT() { RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN; }
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
#elif defined(STM32F091xC)
#define WRITE_DELAY { }
#define READ_DELAY { RD_ACTIVE; }
#define GPIO_INIT() { RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN; }
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
#elif defined(STM32F303xE)
#define WRITE_DELAY { }
#define READ_DELAY { RD_ACTIVE; }
#define GPIO_INIT() { RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN; \
/* AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_1; */ }
#elif defined(STM32F401xE)
#define WRITE_DELAY { WR_ACTIVE; WR_ACTIVE; }
#define READ_DELAY { RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; }
#define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN; }
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
#elif defined(STM32F411xE)
#define WRITE_DELAY { WR_ACTIVE; WR_ACTIVE; WR_ACTIVE; }
#define READ_DELAY { RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; }
#define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN; }
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
#elif defined(STM32L053xx)
#define WRITE_DELAY { }
#define READ_DELAY { RD_ACTIVE; }
#define GPIO_INIT() { RCC->IOPENR |= RCC_IOPENR_GPIOAEN | RCC_IOPENR_GPIOBEN | RCC_IOPENR_GPIOCEN; }
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
#elif defined(STM32L476xx)
#define WRITE_DELAY { WR_ACTIVE; WR_ACTIVE; }
#define READ_DELAY { RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; }
#define GPIO_INIT() { RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOBEN | RCC_AHB2ENR_GPIOCEN; }
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
#elif defined(STM32F401xE) || defined(STM32F411xE)
#define WRITE_DELAY { WR_ACTIVE; WR_ACTIVE; }
#define READ_DELAY { RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; }
#define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN; }
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
#else
#error unsupported STM32
#endif
#if 0
#elif defined(ARDUINO_GENERIC_STM32F103C) || defined(ARDUINO_NUCLEO_F103C8)
#elif defined(ARDUINO_GENERIC_STM32F103C) || defined(ARDUINO_NUCLEO_F103C8) || defined(ARDUINO_BLUEPILL_F103C8)
#warning Uno Shield on BLUEPILL
#define RD_PORT GPIOB
#define RD_PIN 5
//#define RD_PIN 0 //hardware mod to Adapter. Allows use of PB5 for SD Card
//#define RD_PIN 5
#define RD_PIN 0 //hardware mod to Adapter. Allows use of PB5 for SD Card
#define WR_PORT GPIOB
#define WR_PIN 6
#define CD_PORT GPIOB
@@ -417,7 +450,7 @@ void write_8(uint8_t x)
#define setWriteDir() {GP_OUT(GPIOA, CRL, 0xFFFFFFFF); }
#define setReadDir() {GP_INP(GPIOA, CRL, 0xFFFFFFFF); }
#elif IS_NUCLEO // Uno Shield on NUCLEO
#elif IS_NUCLEO64 // Uno Shield on NUCLEO
#warning Uno Shield on NUCLEO
#define RD_PORT GPIOA
#define RD_PIN 0

3
utility/pin_shield_1.h
View File

@@ -105,7 +105,8 @@
#define D13_PORT GPIOB
#define D13_PIN 13 //3
#define A0_PORT GPIOB
#define A0_PIN 5
#define A0_PIN 5 //original pcb uses SPI pin
// #define A0_PIN 0 //hardware mod to Adapter to PB0. Allows use of PB5 for SD Card
#define A1_PORT GPIOB
#define A1_PIN 6
#define A2_PORT GPIOB