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MCUFRIEND_kbv/utility/mcufriend_shield.h

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disable SPECIAL for merge
2018-06-15 09:18:54 +01:00
//#define USE_SPECIAL //check for custom drivers
start off commit
2016-03-15 21:03:51 +00:00
simplify XX_DELAY macros
2018-06-08 20:56:31 +01:00
#define WR_ACTIVE2 {WR_ACTIVE; WR_ACTIVE;}
#define WR_ACTIVE4 {WR_ACTIVE2; WR_ACTIVE2;}
#define WR_ACTIVE8 {WR_ACTIVE4; WR_ACTIVE4;}
#define RD_ACTIVE2 {RD_ACTIVE; RD_ACTIVE;}
#define RD_ACTIVE4 {RD_ACTIVE2; RD_ACTIVE2;}
#define RD_ACTIVE8 {RD_ACTIVE4; RD_ACTIVE4;}
#define RD_ACTIVE16 {RD_ACTIVE8; RD_ACTIVE8;}
WR_IDLE macros
2018-07-17 09:54:50 +01:00
#define WR_IDLE2 {WR_IDLE; WR_IDLE;}
#define WR_IDLE4 {WR_IDLE2; WR_IDLE2;}
Init all the GPIO ports. Adjust read timing.
2018-12-12 21:20:32 +00:00
#define RD_IDLE2 {RD_IDLE; RD_IDLE;}
#define RD_IDLE4 {RD_IDLE2; RD_IDLE2;}
simplify XX_DELAY macros
2018-06-08 20:56:31 +01:00
simplify SPECIAL delays
2018-06-11 21:28:03 +01:00
#if defined(USE_SPECIAL)
#include "mcufriend_special.h"
#if !defined(USE_SPECIAL_FAIL)
#warning WE ARE USING A SPECIAL CUSTOM DRIVER
#endif
#endif
#if !defined(USE_SPECIAL) || defined (USE_SPECIAL_FAIL)
start off commit
2016-03-15 21:03:51 +00:00
#if 0
add driver for mega1284P Bobuino
2017-12-31 21:16:48 +00:00
//################################### UNO ##############################
run on XMINI-328PB
2019-03-02 09:35:43 +00:00
#elif defined(__AVR_ATmega328P__) || defined(__AVR_ATmega328PB__) //regular UNO shield on UNO
add some wiring schemes
2020-09-13 22:42:39 +01:00
//LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST|
//AVR pin |PD7|PD6|PD5|PD4|PD3|PD2|PB1|PB0| |PC0|PC1|PC2|PC3|PC4|
add Shield header pin numbers for Uno and Teensy4.x
2021-01-18 12:14:27 +00:00
//UNO pins |7 |6 |5 |4 |3 |2 |9 |8 | |A0 |A1 |A2 |A3 |A4 |
start off commit
2016-03-15 21:03:51 +00:00
#define RD_PORT PORTC
#define RD_PIN 0
#define WR_PORT PORTC
#define WR_PIN 1
#define CD_PORT PORTC
#define CD_PIN 2
#define CS_PORT PORTC
#define CS_PIN 3
#define RESET_PORT PORTC
#define RESET_PIN 4
intuitive macros
2017-02-01 21:10:39 +00:00
#define BMASK 0x03 //more intuitive style for mixed Ports
#define DMASK 0xFC //does exactly the same as previous
#define write_8(x) { PORTB = (PORTB & ~BMASK) | ((x) & BMASK); PORTD = (PORTD & ~DMASK) | ((x) & DMASK); }
#define read_8() ( (PINB & BMASK) | (PIND & DMASK) )
#define setWriteDir() { DDRB |= BMASK; DDRD |= DMASK; }
#define setReadDir() { DDRB &= ~BMASK; DDRD &= ~DMASK; }
start off commit
2016-03-15 21:03:51 +00:00
#define write8(x) { write_8(x); WR_STROBE; }
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
#define PIN_LOW(p, b) (p) &= ~(1<<(b))
#define PIN_HIGH(p, b) (p) |= (1<<(b))
#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
add driver for mega1284P Bobuino
2017-12-31 21:16:48 +00:00
//################################### MEGA2560 ##############################
add mega1280
2016-04-16 20:23:36 +01:00
#elif defined(__AVR_ATmega2560__) || defined(__AVR_ATmega1280__) //regular UNO shield on MEGA2560
add some wiring schemes
2020-09-13 22:42:39 +01:00
//LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST|
//AVR pin |PH4|PH3|PE3|PG5|PE5|PE4|PH6|PH5| |PF0|PF1|PF2|PF3|PF4|
start off commit
2016-03-15 21:03:51 +00:00
#define RD_PORT PORTF
#define RD_PIN 0
#define WR_PORT PORTF
#define WR_PIN 1
#define CD_PORT PORTF
#define CD_PIN 2
#define CS_PORT PORTF
#define CS_PIN 3
#define RESET_PORT PORTF
#define RESET_PIN 4
#define EMASK 0x38
#define GMASK 0x20
#define HMASK 0x78
#define write_8(x) { PORTH &= ~HMASK; PORTG &= ~GMASK; PORTE &= ~EMASK; \
PORTH |= (((x) & (3<<0)) << 5); \
PORTE |= (((x) & (3<<2)) << 2); \
PORTG |= (((x) & (1<<4)) << 1); \
PORTE |= (((x) & (1<<5)) >> 2); \
PORTH |= (((x) & (3<<6)) >> 3); \
}
#define read_8() ( ((PINH & (3<<5)) >> 5)\
| ((PINE & (3<<4)) >> 2)\
| ((PING & (1<<5)) >> 1)\
| ((PINE & (1<<3)) << 2)\
| ((PINH & (3<<3)) << 3)\
)
#define setWriteDir() { DDRH |= HMASK; DDRG |= GMASK; DDRE |= EMASK; }
#define setReadDir() { DDRH &= ~HMASK; DDRG &= ~GMASK; DDRE &= ~EMASK; }
#define write8(x) { write_8(x); WR_STROBE; }
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
#define PIN_LOW(p, b) (p) &= ~(1<<(b))
#define PIN_HIGH(p, b) (p) |= (1<<(b))
#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
add support for Thinary EVERY-mega4808
2019-09-07 23:16:42 +01:00
//################################### MEGA4809 NANO_EVERY 4808 ##############################
#elif defined(__AVR_ATmega4808__) // Thinary EVERY-4808 with Nano-Shield_Adapter
#warning EVERY-4808 with Nano-Shield_Adapter
#define RD_PORT VPORTD //
#define RD_PIN 0
#define WR_PORT VPORTD
#define WR_PIN 1
#define CD_PORT VPORTD
#define CD_PIN 2
#define CS_PORT VPORTD
#define CS_PIN 3
#define RESET_PORT VPORTF
#define RESET_PIN 2
#define AMASK 0xFF
#define write_8(x) { VPORTA.OUT = ((x) << 6) | ((x) >> 2); }
#define read_8() ( (VPORTA.IN >> 6) | (VPORTA.IN << 2) )
#define setWriteDir() { VPORTA_DIR |= AMASK; }
#define setReadDir() { VPORTA_DIR &= ~AMASK; }
//#define WRITE_DELAY { WR_ACTIVE; WR_ACTIVE; } //6.47s no_inline
#define WRITE_DELAY { WR_ACTIVE2; WR_ACTIVE; } //-Os=5.43s @20MHz always_inline. (-O1=5.41s, -O3=5.25s)
#define READ_DELAY { RD_ACTIVE4; } //ID=0x7789
#define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; }
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; }
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
#define PIN_LOW(p, b) (p).OUT &= ~(1<<(b))
#define PIN_HIGH(p, b) (p).OUT |= (1<<(b))
#define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b))
add UNO_WIFI_REV2
2020-05-28 10:36:56 +01:00
//########################## MEGA4809 NANO_EVERY or UNO_WIFI_REV2 ##############################
#elif defined(__AVR_ATmega4809__) && (defined(ARDUINO_AVR_NANO_EVERY) || defined(ARDUINO_AVR_UNO_WIFI_REV2))
#if defined(ARDUINO_AVR_NANO_EVERY)
EVERY-4809 with Nano-Shield_Adapter
2019-06-30 09:57:22 +01:00
#warning EVERY-4809 with Nano-Shield_Adapter using VPORT.OUT and BLD/BST
add some wiring schemes
2020-09-13 22:42:39 +01:00
//LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST|
//AVR pin |PA1|PF4|PB2|PC6|PF5|PA0|PB0|PE3| |PD3|PD2|PD1|PD0|PF2|
EVERY-4809 with Nano-Shield_Adapter
2019-06-30 09:57:22 +01:00
#define RD_PORT VPORTD //
#define RD_PIN 3
#define WR_PORT VPORTD
#define WR_PIN 2
#define CD_PORT VPORTD
#define CD_PIN 1
#define CS_PORT VPORTD
#define CS_PIN 0
#define RESET_PORT VPORTF
#define RESET_PIN 2
add UNO_WIFI_REV2
2020-05-28 10:36:56 +01:00
#elif defined(ARDUINO_AVR_UNO_WIFI_REV2)
#warning UNO_WIFI_REV2 using VPORT.OUT and BLD/BST
#define RD_PORT VPORTD //
#define RD_PIN 0
#define WR_PORT VPORTD
#define WR_PIN 1
#define CD_PORT VPORTD
#define CD_PIN 2
#define CS_PORT VPORTD
#define CS_PIN 3
#define RESET_PORT VPORTD
#define RESET_PIN 4
#endif
EVERY-4809 with Nano-Shield_Adapter
2019-06-30 09:57:22 +01:00
#define AMASK (3<<0)
#define BMASK (5<<0)
#define CMASK (1<<6)
#define EMASK (1<<3)
#define FMASK (3<<4)
static __attribute((always_inline))
void write_8(uint8_t val)
{
asm volatile("in __tmp_reg__,0x01" "\n\t" //VPORTA.OUT
"BST %0,2" "\n\t" "BLD __tmp_reg__,0" "\n\t"
"BST %0,7" "\n\t" "BLD __tmp_reg__,1" "\n\t"
"out 0x01,__tmp_reg__" : : "a" (val));
asm volatile("in __tmp_reg__,0x05" "\n\t" //VPORTB.OUT
"BST %0,1" "\n\t" "BLD __tmp_reg__,0" "\n\t"
"BST %0,5" "\n\t" "BLD __tmp_reg__,2" "\n\t"
"out 0x05,__tmp_reg__" : : "a" (val));
asm volatile("in __tmp_reg__,0x09" "\n\t" //VPORTC.OUT
"BST %0,4" "\n\t" "BLD __tmp_reg__,6" "\n\t"
"out 0x09,__tmp_reg__" : : "a" (val));
asm volatile("in __tmp_reg__,0x11" "\n\t" //VPORTE.OUT
"BST %0,0" "\n\t" "BLD __tmp_reg__,3" "\n\t"
"out 0x11,__tmp_reg__" : : "a" (val));
asm volatile("in __tmp_reg__,0x15" "\n\t" //VPORTF.OUT
"BST %0,3" "\n\t" "BLD __tmp_reg__,5" "\n\t"
"BST %0,6" "\n\t" "BLD __tmp_reg__,4" "\n\t"
"out 0x15,__tmp_reg__" : : "a" (val));
}
#define read_8() ( 0 \
| ((VPORTA_IN & (1<<0)) << 2)\
| ((VPORTA_IN & (1<<1)) << 6)\
| ((VPORTB_IN & (1<<0)) << 1)\
| ((VPORTB_IN & (1<<2)) << 3)\
| ((VPORTC_IN & CMASK) >> 2)\
| ((VPORTE_IN & EMASK) >> 3)\
| ((VPORTF_IN & (1<<5)) >> 2)\
| ((VPORTF_IN & (1<<4)) << 2)\
)
#define setWriteDir() { VPORTA_DIR |= AMASK; VPORTB_DIR |= BMASK; VPORTC_DIR |= CMASK; VPORTE_DIR |= EMASK; VPORTF_DIR |= FMASK; }
#define setReadDir() { VPORTA_DIR &= ~AMASK; VPORTB_DIR &= ~BMASK; VPORTC_DIR &= ~CMASK; VPORTE_DIR &= ~EMASK; VPORTF_DIR &= ~FMASK; }
//#define WRITE_DELAY { WR_ACTIVE; WR_ACTIVE; } //6.47s no_inline
#define WRITE_DELAY { WR_ACTIVE2; WR_ACTIVE; } //-Os=5.43s @20MHz always_inline. (-O1=5.41s, -O3=5.25s)
#define READ_DELAY { RD_ACTIVE4; } //ID=0x7789
#define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; }
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; }
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
#define PIN_LOW(p, b) (p).OUT &= ~(1<<(b))
#define PIN_HIGH(p, b) (p).OUT |= (1<<(b))
#define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b))
support Teensy++ 2.0 (thanks tysonlt)
2019-02-03 12:13:28 +00:00
//################################### TEENSY++2.0 ##############################
#elif defined(__AVR_AT90USB1286__) //regular UNO shield on TEENSY++ 2.0 thanks tysonlt
Add standard wiring info
2019-03-26 12:40:04 +00:00
//LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST|
//AVR pin |PD7|PD6|PD5|PD4|PD3|PD2|PE1|PE0| |PF0|PF1|PF2|PF3|PF4|
support Teensy++ 2.0 (thanks tysonlt)
2019-02-03 12:13:28 +00:00
#define RD_PORT PORTF
#define RD_PIN 0
#define WR_PORT PORTF
#define WR_PIN 1
#define CD_PORT PORTF
#define CD_PIN 2
#define CS_PORT PORTF
#define CS_PIN 3
#define RESET_PORT PORTF
#define RESET_PIN 4
#define EMASK 0x03 //more intuitive style for mixed Ports
#define DMASK 0xFC //does exactly the same as previous
#define write_8(x) { PORTE = (PORTE & ~EMASK) | ((x) & EMASK); PORTD = (PORTD & ~DMASK) | ((x) & DMASK); }
#define read_8() ( (PINE & EMASK) | (PIND & DMASK) )
#define setWriteDir() { DDRE |= EMASK; DDRD |= DMASK; }
#define setReadDir() { DDRE &= ~EMASK; DDRD &= ~DMASK; }
#define write8(x) { write_8(x); WR_STROBE; }
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
#define PIN_LOW(p, b) (p) &= ~(1<<(b))
#define PIN_HIGH(p, b) (p) |= (1<<(b))
#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
tidy up STM32F103, conditional GPIO_INIT macro
2017-03-27 16:38:55 +01:00
//################################# ZERO and M0_PRO ############################
start off commit
2016-03-15 21:03:51 +00:00
#elif defined(__SAMD21G18A__) //regular UNO shield on ZERO or M0_PRO
#include "sam.h"
// configure macros for the control pins
#define RD_PORT PORT->Group[0]
#define RD_PIN 2
#define WR_PORT PORT->Group[1]
#define WR_PIN 8
#define CD_PORT PORT->Group[1]
#define CD_PIN 9
#define CS_PORT PORT->Group[0]
#define CS_PIN 4
#define RESET_PORT PORT->Group[0]
#define RESET_PIN 5
// configure macros for data bus
#define DMASK 0x0030C3C0
// #define write_8(x) PORT->Group[0].OUT.reg = (PORT->Group[0].OUT.reg & ~DMASK)|(((x) & 0x0F) << 6)|(((x) & 0x30) << 10)|(((x) & 0xC0)<<14)
change ZERO vs M0 conditional
2022-08-30 19:02:29 +01:00
#if defined(ARDUINO_SAMD_ZERO) && !defined(USE_M0_PINOUT) // American ZERO
port pin wiring for Zero and M0 Pro
2020-03-02 15:34:49 +00:00
//LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST |
Oops. My Zero and M0 pin mapping had typos
2021-12-12 12:24:13 +00:00
//SAMD21 pin |PA21|PA20|PA15|PA8 |PA9 |PA14|PA7 |PA6 | |PA2|PB8|PB9 |PA4 |PA5 |
start off commit
2016-03-15 21:03:51 +00:00
#define write_8(x) {\
PORT->Group[0].OUTCLR.reg = DMASK;\
PORT->Group[0].OUTSET.reg = (((x) & 0x0B) << 6)\
|(((x) & (1<<2)) << 12)\
|(((x) & (1<<4)) << 4)\
|(((x) & (1<<5)) << 10)\
|(((x) & 0xC0) << 14);\
}
#define read_8() (((PORT->Group[0].IN.reg >> 6) & 0x0B)\
|((PORT->Group[0].IN.reg >> 12) & (1<<2))\
|((PORT->Group[0].IN.reg >> 4) & (1<<4))\
|((PORT->Group[0].IN.reg >> 10) & (1<<5))\
|((PORT->Group[0].IN.reg >> 14) & 0xC0))
#else //default to an M0_PRO on v1.6.5 or 1.7.6
port pin wiring for Zero and M0 Pro
2020-03-02 15:34:49 +00:00
//LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST |
Oops. My Zero and M0 pin mapping had typos
2021-12-12 12:24:13 +00:00
//SAMD21 pin |PA21|PA20|PA15|PA14|PA9 |PA8 |PA7 |PA6 | |PA2|PB8|PB9 |PA4 |PA5 |
start off commit
2016-03-15 21:03:51 +00:00
#define write_8(x) {\
PORT->Group[0].OUTCLR.reg = DMASK;\
PORT->Group[0].OUTSET.reg = (((x) & 0x0F) << 6)\
|(((x) & 0x30) << 10)\
|(((x) & 0xC0) << 14);\
}
#define read_8() (((PORT->Group[0].IN.reg >> 6) & 0x0F)|((PORT->Group[0].IN.reg >> 10) & 0x30)|((PORT->Group[0].IN.reg >> 14) & 0xC0))
#endif
#define setWriteDir() { PORT->Group[0].DIRSET.reg = DMASK; \
PORT->Group[0].WRCONFIG.reg = (DMASK & 0xFFFF) | (0<<22) | (1<<28) | (1<<30); \
PORT->Group[0].WRCONFIG.reg = (DMASK>>16) | (0<<22) | (1<<28) | (1<<30) | (1<<31); \
}
#define setReadDir() { PORT->Group[0].DIRCLR.reg = DMASK; \
PORT->Group[0].WRCONFIG.reg = (DMASK & 0xFFFF) | (1<<17) | (1<<28) | (1<<30); \
PORT->Group[0].WRCONFIG.reg = (DMASK>>16) | (1<<17) | (1<<28) | (1<<30) | (1<<31); \
}
add write delay for ZERO, add macros for NUCLEO-STM32F103
2016-11-15 11:49:56 +00:00
#define write8(x) { write_8(x); WR_ACTIVE; WR_STROBE; }
start off commit
2016-03-15 21:03:51 +00:00
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
// Shield Control macros.
#define PIN_LOW(port, pin) (port).OUTCLR.reg = (1<<(pin))
#define PIN_HIGH(port, pin) (port).OUTSET.reg = (1<<(pin))
#define PIN_OUTPUT(port, pin) (port).DIR.reg |= (1<<(pin))
support GRAND CENTRAL M4
2020-01-13 09:19:20 +00:00
//####################################### GRAND CENTRAL M4 ############################
#elif defined(__SAMD51P20A__) //regular UNO shield on GRAND CENTRAL M4
//LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST|
//SAMD51 pin |PD21|PD20|PC21|PC20|PC19|PC18|PB2|PB18| |PA2|PA5|PB3|PC0|PC1|
#define WRITE_DELAY { WR_ACTIVE4; }
#define IDLE_DELAY { WR_IDLE2; }
#define READ_DELAY { RD_ACTIVE8;}
// configure macros for the control pins
#define RD_PORT PORT->Group[0]
#define RD_PIN 2
#define WR_PORT PORT->Group[0]
#define WR_PIN 5
#define CD_PORT PORT->Group[1]
#define CD_PIN 3
#define CS_PORT PORT->Group[2]
#define CS_PIN 0
#define RESET_PORT PORT->Group[2]
#define RESET_PIN 1
// configure macros for data bus
#define BMASK ((1<<18)|(1<<2)) //BMASK has bits in H and L for WRCONFIG
#define CMASK (0x0F << 18) //CMASK only has bits in H
#define DMASK (0x03 << 20)
#define WRMASK ((0<<22) | (1<<28) | (1<<30)) //
#define RDMASK ((1<<17) | (1<<28) | (1<<30)) //
#define write_8(x) { PORT->Group[1].OUTCLR.reg = BMASK; PORT->Group[2].OUTCLR.reg = CMASK; PORT->Group[3].OUTCLR.reg = DMASK; \
PORT->Group[1].OUTSET.reg = (((x) & (1<<0)) << 18) | (((x) & (1<<1)) << 1); \
PORT->Group[2].OUTSET.reg = (((x) & (15<<2)) << 16); \
PORT->Group[3].OUTSET.reg = (((x) & (3<<6)) << 14); \
}
#define read_8() ( ((PORT->Group[1].IN.reg & (1<<18)) >> 18)\
| ((PORT->Group[1].IN.reg & (1<<2)) >> 1)\
| ((PORT->Group[2].IN.reg & (15<<18)) >> 16)\
| ((PORT->Group[3].IN.reg & (3<<20)) >> 14)\
)
#define setWriteDir() { \
PORT->Group[1].DIRSET.reg = BMASK; \
PORT->Group[1].WRCONFIG.reg = (BMASK & 0xFFFF) | WRMASK; \
PORT->Group[1].WRCONFIG.reg = (BMASK >> 16) | WRMASK | (1<<31); \
PORT->Group[2].DIRSET.reg = CMASK; \
PORT->Group[2].WRCONFIG.reg = (CMASK >> 16) | WRMASK | (1<<31); \
PORT->Group[3].DIRSET.reg = DMASK; \
PORT->Group[3].WRCONFIG.reg = (DMASK >> 16) | WRMASK | (1<<31); \
}
#define setReadDir() { \
PORT->Group[1].DIRCLR.reg = BMASK; \
PORT->Group[1].WRCONFIG.reg = (BMASK & 0xFFFF) | RDMASK; \
PORT->Group[1].WRCONFIG.reg = (BMASK >> 16) | RDMASK | (1<<31); \
PORT->Group[2].DIRCLR.reg = CMASK; \
PORT->Group[2].WRCONFIG.reg = (CMASK >> 16) | RDMASK | (1<<31); \
PORT->Group[3].DIRCLR.reg = DMASK; \
PORT->Group[3].WRCONFIG.reg = (DMASK >> 16) | RDMASK | (1<<31); \
}
#define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; IDLE_DELAY; }
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE2; RD_IDLE; }
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
// Shield Control macros.
#define PIN_LOW(port, pin) (port).OUTCLR.reg = (1<<(pin))
#define PIN_HIGH(port, pin) (port).OUTSET.reg = (1<<(pin))
#define PIN_OUTPUT(port, pin) (port).DIRSET.reg = (1<<(pin))
tidy up STM32F103, conditional GPIO_INIT macro
2017-03-27 16:38:55 +01:00
//####################################### DUE ############################
start off commit
2016-03-15 21:03:51 +00:00
#elif defined(__SAM3X8E__) //regular UNO shield on DUE
add some wiring schemes
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//LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST |
//SAM3XE pin |PC23|PC24|PC25|PC26|PC28|PB25|PC21|PC22| |PA16|PA24|PA23|PA22|PA6 |
rearrange Due timing macros. add extra WR_IDLE for Due
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#define WRITE_DELAY { WR_ACTIVE; }
#define IDLE_DELAY { WR_IDLE; }
#define READ_DELAY { RD_ACTIVE;}
start off commit
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// configure macros for the control pins
#define RD_PORT PIOA
#define RD_PIN 16
#define WR_PORT PIOA
#define WR_PIN 24
#define CD_PORT PIOA
#define CD_PIN 23
#define CS_PORT PIOA
#define CS_PIN 22
#define RESET_PORT PIOA
#define RESET_PIN 6
// configure macros for data bus
#define BMASK (1<<25)
#define CMASK (0xBF << 21)
#define write_8(x) { PIOB->PIO_CODR = BMASK; PIOC->PIO_CODR = CMASK; \
PIOB->PIO_SODR = (((x) & (1<<2)) << 23); \
faster on Due. 2.11s v 3.84s
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PIOC->PIO_SODR = (((x) & (1<<0)) << 22) \
| (((x) & (1<<1)) << 20) \
| (((x) & (1<<3)) << 25) \
| (((x) & (1<<4)) << 22) \
| (((x) & (1<<5)) << 20) \
| (((x) & (1<<6)) << 18) \
| (((x) & (1<<7)) << 16); \
start off commit
2016-03-15 21:03:51 +00:00
}
#define read_8() ( ((PIOC->PIO_PDSR & (1<<22)) >> 22)\
| ((PIOC->PIO_PDSR & (1<<21)) >> 20)\
| ((PIOB->PIO_PDSR & (1<<25)) >> 23)\
| ((PIOC->PIO_PDSR & (1<<28)) >> 25)\
| ((PIOC->PIO_PDSR & (1<<26)) >> 22)\
| ((PIOC->PIO_PDSR & (1<<25)) >> 20)\
| ((PIOC->PIO_PDSR & (1<<24)) >> 18)\
| ((PIOC->PIO_PDSR & (1<<23)) >> 16)\
)
#define setWriteDir() { PIOB->PIO_OER = BMASK; PIOC->PIO_OER = CMASK; }
#define setReadDir() { \
PMC->PMC_PCER0 = (1 << ID_PIOB)|(1 << ID_PIOC);\
PIOB->PIO_ODR = BMASK; PIOC->PIO_ODR = CMASK;\
}
rearrange Due timing macros. add extra WR_IDLE for Due
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#define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; IDLE_DELAY; }
start off commit
2016-03-15 21:03:51 +00:00
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
rearrange Due timing macros. add extra WR_IDLE for Due
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#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; RD_IDLE; }
start off commit
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#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
rearrange Due timing macros. add extra WR_IDLE for Due
2018-10-09 10:36:37 +01:00
start off commit
2016-03-15 21:03:51 +00:00
// Shield Control macros.
#define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin))
#define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin))
#define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin))
add driver for mega1284P Bobuino
2017-12-31 21:16:48 +00:00
//################################### LEONARDO ##############################
start off commit
2016-03-15 21:03:51 +00:00
#elif defined(__AVR_ATmega32U4__) //regular UNO shield on Leonardo
add some wiring schemes
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//LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST|
//AVR pin |PE6|PD7|PC6|PD4|PD0|PD1|PB5|PB4| |PF7|PF6|PF5|PF4|PF1|
start off commit
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#define RD_PORT PORTF
#define RD_PIN 7
#define WR_PORT PORTF
#define WR_PIN 6
#define CD_PORT PORTF
#define CD_PIN 5
#define CS_PORT PORTF
#define CS_PIN 4
#define RESET_PORT PORTF
#define RESET_PIN 1
#define BMASK (3<<4)
#define CMASK (1<<6)
#define DMASK ((1<<7)|(1<<4)|(3<<0))
#define EMASK (1<<6)
static inline //hope we use r24
void write_8(uint8_t x)
{
PORTB &= ~BMASK;
PORTC &= ~CMASK;
PORTD &= ~DMASK;
PORTE &= ~EMASK;
PORTB |= (((x) & (3 << 0)) << 4);
PORTD |= (((x) & (1 << 2)) >> 1);
PORTD |= (((x) & (1 << 3)) >> 3);
PORTD |= (((x) & (1 << 4)) << 0);
PORTC |= (((x) & (1 << 5)) << 1);
PORTD |= (((x) & (1 << 6)) << 1);
PORTE |= (((x) & (1 << 7)) >> 1);
}
#define read_8() ( ((PINB & (3<<4)) >> 4)\
| ((PIND & (1<<1)) << 1)\
| ((PIND & (1<<0)) << 3)\
| ((PIND & (1<<4)) >> 0)\
| ((PINC & (1<<6)) >> 1)\
| ((PIND & (1<<7)) >> 1)\
| ((PINE & (1<<6)) << 1)\
)
#define setWriteDir() { DDRB |= BMASK; DDRC |= CMASK; DDRD |= DMASK; DDRE |= EMASK; }
#define setReadDir() { DDRB &= ~BMASK; DDRC &= ~CMASK; DDRD &= ~DMASK; DDRE &= ~EMASK; }
#define write8(x) { write_8(x); WR_STROBE; }
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
#define PIN_LOW(p, b) (p) &= ~(1<<(b))
#define PIN_HIGH(p, b) (p) |= (1<<(b))
#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
add driver for mega1284P Bobuino
2017-12-31 21:16:48 +00:00
//################################### UNO SHIELD on BOBUINO ##############################
#elif defined(__AVR_ATmega1284P__) || defined(__AVR_ATmega644P__) //UNO shield on BOBUINO
#warning regular UNO shield on BOBUINO
Add standard wiring info
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//LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST|
//AVR pin |PB3|PB2|PB1|PB0|PD3|PD2|PD6|PD5| |PA7|PA6|PA5|PA4|PA3|
add driver for mega1284P Bobuino
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#define RD_PORT PORTA
#define RD_PIN 7
#define WR_PORT PORTA
#define WR_PIN 6
#define CD_PORT PORTA
#define CD_PIN 5
#define CS_PORT PORTA
#define CS_PIN 4
#define RESET_PORT PORTA
#define RESET_PIN 3
#define BMASK 0x0F //
#define DMASK 0x6C //
#define write_8(x) { PORTB = (PORTB & ~BMASK) | ((x) >> 4); \
PORTD = (PORTD & ~DMASK) | ((x) & 0x0C) | (((x) & 0x03) << 5); }
#define read_8() ( (PINB << 4) | (PIND & 0x0C) | ((PIND & 0x60) >> 5) )
#define setWriteDir() { DDRB |= BMASK; DDRD |= DMASK; }
#define setReadDir() { DDRB &= ~BMASK; DDRD &= ~DMASK; }
#define write8(x) { write_8(x); WR_STROBE; }
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
#define PIN_LOW(p, b) (p) &= ~(1<<(b))
#define PIN_HIGH(p, b) (p) |= (1<<(b))
#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
Add support for Teensy 4.0
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//####################################### TEENSY 4.0 ############################
#elif defined(__IMXRT1062__) // regular UNO shield on a Teensy 4.x
#warning regular UNO shield on a Teensy 4.0
//LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST | A5
//MXRT pin |7.17|7.10|9.8|9.6|9.5|9.4|7.11|7.16| |6.18|6.19|6.23|6.22|6.17|6.16
add Shield header pin numbers for Uno and Teensy4.x
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//4.x pins |7 |6 |5 |4 |3 |2 |9 |8 | |14 |15 |16 |17 |18 |
Add support for Teensy 4.0
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#if 0
#elif defined(__IMXRT1062__)
#define WRITE_DELAY { WR_ACTIVE8;WR_ACTIVE8; }
#define IDLE_DELAY { WR_IDLE2;WR_IDLE; }
#define READ_DELAY { RD_ACTIVE16;RD_ACTIVE16; }
#else
#error unspecified delays
#endif
#define RD_PORT GPIO6
#define RD_PIN 18
#define WR_PORT GPIO6
#define WR_PIN 19
#define CD_PORT GPIO6
#define CD_PIN 23
#define CS_PORT GPIO6
#define CS_PIN 22
#define RESET_PORT GPIO6
#define RESET_PIN 17
// configure macros for the data pins
#define GMASK ((1<<17)|(1<<10)|(1<<11)|(1<<16))
#define IMASK ((1<<8)|(1<<6)|(1<<5)|(1<<4))
#define write_8(d) { \
GPIO7_DR_CLEAR = GMASK; GPIO9_DR_CLEAR = IMASK; \
GPIO7_DR_SET = (((d) & (1 << 0)) << 16) \
| (((d) & (1 << 1)) << 10) \
| (((d) & (1 << 6)) << 4) \
| (((d) & (1 << 7)) << 10); \
GPIO9_DR_SET = (((d) & (1 << 2)) << 2) \
| (((d) & (1 << 3)) << 2) \
| (((d) & (1 << 4)) << 2) \
| (((d) & (1 << 5)) << 3); \
}
#define read_8() ((((GPIO7_PSR & (1 << 16)) >> 16) \
| ((GPIO7_PSR & (1 << 11)) >> 10) \
| ((GPIO9_PSR & (1 << 4)) >> 2) \
| ((GPIO9_PSR & (1 << 5)) >> 2) \
| ((GPIO9_PSR & (1 << 6)) >> 2) \
| ((GPIO9_PSR & (1 << 8)) >> 3) \
| ((GPIO7_PSR & (1 << 10)) >> 4) \
| ((GPIO7_PSR & (1 << 17)) >> 10)))
#define setWriteDir() {GPIO7_GDIR |= GMASK;GPIO9_GDIR |= IMASK; }
#define setReadDir() {GPIO7_GDIR &= ~GMASK;GPIO9_GDIR &= ~IMASK; }
#define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; IDLE_DELAY; }
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE2; RD_IDLE; }
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
#define GPIO_INIT() {for (int i = 2; i <= 9; i++) pinMode(i, OUTPUT); for (int i = A0; i <= A4; i++) pinMode(i, OUTPUT);}
#define PASTE(x, y) x ## y
#define PIN_LOW(port, pin) PASTE(port, _DR_CLEAR) = (1<<(pin))
#define PIN_HIGH(port, pin) PASTE(port, _DR_SET) = (1<<(pin))
#define PIN_OUTPUT(port, pin) PASTE(port, _GDIR) |= (1<<(pin))
add TeensyLC Shield. Thanks DaveLapp.
2021-05-18 16:30:35 +01:00
//################################ TEENSY 3.x and LC ############################
#elif defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MK64FX512__) || defined(__MK66FX1M0__) || defined(__MKL26Z64__)
#warning regular UNO shield on a Teensy 3.x or LC
Add Uno Shield on Teensy 3.5, 3.6. 3.6 needs testing
2017-02-13 09:01:50 +00:00
Add standard wiring info
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//LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST|
add TeensyLC Shield. Thanks DaveLapp.
2021-05-18 16:30:35 +01:00
//MK20,64,66|PD2|PD4|PD7|PA13|PA12|PD0|PC3|PD3| |PD1|PC0|PB0|PB1|PB3|
//MKL26Z prt|PD2|PD4|PD7|PA2 |PA1 |PD0|PC3|PD3| |PD1|PC0|PB0|PB1|PB3|
Fix teensy 3.x pin typo and add 3.6 pin configuration (#154)
2020-10-01 23:26:31 +02:00
//3.6 pins |7 |6 |5 |4 |3 |2 |9 |8 | |14 |15 |16 |17 |18 |
Add standard wiring info
2019-03-26 12:40:04 +00:00
add TeensyLC Shield. Thanks DaveLapp.
2021-05-18 16:30:35 +01:00
#if 0
#elif defined(__MKL26Z64__) // TeensyLC 48MHz. Thanks DaveLapp
#define WRITE_DELAY { WR_ACTIVE; }
#define IDLE_DELAY { }
#define READ_DELAY { RD_ACTIVE4; }
#elif defined(__MK20DX128__) || defined(__MK20DX256__) // Teensy3.0 || 3.2 96MHz
simplify XX_DELAY macros
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#define WRITE_DELAY { WR_ACTIVE2; }
untested IDLE macros for Teensy
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#define IDLE_DELAY { }
simplify XX_DELAY macros
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#define READ_DELAY { RD_ACTIVE8; RD_ACTIVE; }
Add Uno Shield on Teensy 3.5, 3.6. 3.6 needs testing
2017-02-13 09:01:50 +00:00
#elif defined(__MK64FX512__) // Teensy3.5 120MHz thanks to PeteJohno
simplify XX_DELAY macros
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#define WRITE_DELAY { WR_ACTIVE4; }
untested IDLE macros for Teensy
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#define IDLE_DELAY { WR_IDLE; }
simplify XX_DELAY macros
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#define READ_DELAY { RD_ACTIVE8; }
Add Uno Shield on Teensy 3.5, 3.6. 3.6 needs testing
2017-02-13 09:01:50 +00:00
#elif defined(__MK66FX1M0__) // Teensy3.6 180MHz untested. delays can possibly be reduced.
simplify XX_DELAY macros
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#define WRITE_DELAY { WR_ACTIVE8; }
Add support for Teensy 4.0
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#define IDLE_DELAY { WR_IDLE2; }
simplify XX_DELAY macros
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#define READ_DELAY { RD_ACTIVE16; }
typos
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#else
#error unspecified delays
Add Uno Shield on Teensy 3.5, 3.6. 3.6 needs testing
2017-02-13 09:01:50 +00:00
#endif
support macros for Uno shield on Teensy 3.x
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#define RD_PORT GPIOD
Add Uno Shield on Teensy 3.5, 3.6. 3.6 needs testing
2017-02-13 09:01:50 +00:00
#define RD_PIN 1
support macros for Uno shield on Teensy 3.x
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#define WR_PORT GPIOC
Add Uno Shield on Teensy 3.5, 3.6. 3.6 needs testing
2017-02-13 09:01:50 +00:00
#define WR_PIN 0
support macros for Uno shield on Teensy 3.x
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#define CD_PORT GPIOB
Add Uno Shield on Teensy 3.5, 3.6. 3.6 needs testing
2017-02-13 09:01:50 +00:00
#define CD_PIN 0
support macros for Uno shield on Teensy 3.x
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#define CS_PORT GPIOB
Add Uno Shield on Teensy 3.5, 3.6. 3.6 needs testing
2017-02-13 09:01:50 +00:00
#define CS_PIN 1
support macros for Uno shield on Teensy 3.x
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#define RESET_PORT GPIOB
Add Uno Shield on Teensy 3.5, 3.6. 3.6 needs testing
2017-02-13 09:01:50 +00:00
#define RESET_PIN 3
support macros for Uno shield on Teensy 3.x
2016-08-26 18:09:25 +01:00
// configure macros for the data pins
add TeensyLC Shield. Thanks DaveLapp.
2021-05-18 16:30:35 +01:00
#if defined(__MKL26Z64__) //TeensyLC. Thanks DaveLapp
#define AMASK ((1<<1)|(1<<2)) //PA2,PA1 vs PA13,PA12 on 3.x
#define CMASK ((1<<3))
#define DMASK ((1<<0)|(1<<2)|(1<<3)|(1<<4)|(1<<7))
#define write_8(d) { \
GPIOA_PCOR = AMASK; GPIOC_PCOR = CMASK; GPIOD_PCOR = DMASK; \
GPIOA_PSOR = (((d) & (1 << 3)) >> 2) \
| (((d) & (1 << 4)) >> 2); \
GPIOC_PSOR = (((d) & (1 << 1)) << 2); \
GPIOD_PSOR = (((d) & (1 << 0)) << 3) \
| (((d) & (1 << 2)) >> 2) \
| (((d) & (1 << 5)) << 2) \
| (((d) & (1 << 6)) >> 2) \
| (((d) & (1 << 7)) >> 5); \
}
#define read_8() ((((GPIOD_PDIR & (1<<3)) >> 3) \
| ((GPIOC_PDIR & (1 << 3)) >> 2) \
| ((GPIOD_PDIR & (1 << 0)) << 2) \
| ((GPIOA_PDIR & (1 << 1)) << 2) \
| ((GPIOA_PDIR & (1 << 2)) << 2) \
| ((GPIOD_PDIR & (1 << 7)) >> 2) \
| ((GPIOD_PDIR & (1 << 4)) << 2) \
| ((GPIOD_PDIR & (1 << 2)) << 5)))
#else
support macros for Uno shield on Teensy 3.x
2016-08-26 18:09:25 +01:00
#define AMASK ((1<<12)|(1<<13))
#define CMASK ((1<<3))
#define DMASK ((1<<0)|(1<<2)|(1<<3)|(1<<4)|(1<<7))
Add Uno Shield on Teensy 3.5, 3.6. 3.6 needs testing
2017-02-13 09:01:50 +00:00
#define write_8(d) { \
GPIOA_PCOR = AMASK; GPIOC_PCOR = CMASK; GPIOD_PCOR = DMASK; \
GPIOA_PSOR = (((d) & (1 << 3)) << 9) \
| (((d) & (1 << 4)) << 9); \
GPIOC_PSOR = (((d) & (1 << 1)) << 2); \
GPIOD_PSOR = (((d) & (1 << 0)) << 3) \
| (((d) & (1 << 2)) >> 2) \
| (((d) & (1 << 5)) << 2) \
| (((d) & (1 << 6)) >> 2) \
| (((d) & (1 << 7)) >> 5); \
}
#define read_8() ((((GPIOD_PDIR & (1<<3)) >> 3) \
| ((GPIOC_PDIR & (1 << 3)) >> 2) \
| ((GPIOD_PDIR & (1 << 0)) << 2) \
| ((GPIOA_PDIR & (1 << 12)) >> 9) \
| ((GPIOA_PDIR & (1 << 13)) >> 9) \
| ((GPIOD_PDIR & (1 << 7)) >> 2) \
| ((GPIOD_PDIR & (1 << 4)) << 2) \
| ((GPIOD_PDIR & (1 << 2)) << 5)))
add TeensyLC Shield. Thanks DaveLapp.
2021-05-18 16:30:35 +01:00
#endif
Add Uno Shield on Teensy 3.5, 3.6. 3.6 needs testing
2017-02-13 09:01:50 +00:00
#define setWriteDir() {GPIOA_PDDR |= AMASK;GPIOC_PDDR |= CMASK;GPIOD_PDDR |= DMASK; }
#define setReadDir() {GPIOA_PDDR &= ~AMASK;GPIOC_PDDR &= ~CMASK;GPIOD_PDDR &= ~DMASK; }
Add support for Teensy 4.0
2019-11-30 18:24:02 +00:00
#define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; IDLE_DELAY; }
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; } //PJ adjusted
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
tidy up STM32F103, conditional GPIO_INIT macro
2017-03-27 16:38:55 +01:00
//#define GPIO_INIT() {SIM_SCGC5 |= 0x3E00;} //PORTA-PORTE
#define GPIO_INIT() {for (int i = 2; i <= 9; i++) pinMode(i, OUTPUT); for (int i = A0; i <= A4; i++) pinMode(i, OUTPUT);}
support macros for Uno shield on Teensy 3.x
2016-08-26 18:09:25 +01:00
Add Uno Shield on Teensy 3.5, 3.6. 3.6 needs testing
2017-02-13 09:01:50 +00:00
#define PASTE(x, y) x ## y
support macros for Uno shield on Teensy 3.x
2016-08-26 18:09:25 +01:00
Add Uno Shield on Teensy 3.5, 3.6. 3.6 needs testing
2017-02-13 09:01:50 +00:00
#define PIN_LOW(port, pin) PASTE(port, _PCOR) = (1<<(pin))
#define PIN_HIGH(port, pin) PASTE(port, _PSOR) = (1<<(pin))
support macros for Uno shield on Teensy 3.x
2016-08-26 18:09:25 +01:00
#define PIN_OUTPUT(port, pin) PASTE(port, _PDDR) |= (1<<(pin))
tidy up STM32F103, conditional GPIO_INIT macro
2017-03-27 16:38:55 +01:00
//####################################### STM32 ############################
add NUCLEO_F401RE, NUCLEO_F411RE
2018-01-26 22:02:58 +00:00
// NUCLEO: ARDUINO_NUCLEO_xxxx from ST Core or ARDUINO_STM_NUCLEO_F103RB from MapleCore
new ST Core supports BluePill
2018-04-28 10:33:26 +01:00
// BLUEPILL: ARDUINO_NUCLEO_F103C8 / ARDUINO_BLUEPILL_F103C8 from ST Core or ARDUINO_GENERIC_STM32F103C from MapleCore
add NUCLEO_F401RE, NUCLEO_F411RE
2018-01-26 22:02:58 +00:00
// MAPLE_REV3: n/a from ST Core or ARDUINO_MAPLE_REV3 from MapleCore
// ST Core: ARDUINO_ARCH_STM32
// MapleCore: __STM32F1__
rearrange STM32 shield macros
2018-01-27 00:12:01 +00:00
#elif defined(__STM32F1__) || defined(ARDUINO_ARCH_STM32) //MapleCore or ST Core
nucleo64 shields
2018-04-22 21:04:56 +01:00
#define IS_NUCLEO64 ( defined(ARDUINO_STM_NUCLEO_F103RB) \
|| defined(ARDUINO_NUCLEO_F030R8) || defined(ARDUINO_NUCLEO_F091RC) \
|| defined(ARDUINO_NUCLEO_F103RB) || defined(ARDUINO_NUCLEO_F303RE) \
rearrange STM32 shield macros
2018-01-27 00:12:01 +00:00
|| defined(ARDUINO_NUCLEO_F401RE) || defined(ARDUINO_NUCLEO_F411RE) \
add L152, F446
2018-05-14 22:56:32 +01:00
|| defined(ARDUINO_NUCLEO_F446RE) || defined(ARDUINO_NUCLEO_L053R8) \
|| defined(ARDUINO_NUCLEO_L152RE) || defined(ARDUINO_NUCLEO_L476RG) \
support NUCLEO-F072RB
2019-03-24 23:53:16 +00:00
|| defined(ARDUINO_NUCLEO_F072RB) \
nucleo64 shields
2018-04-22 21:04:56 +01:00
)
added more Nucleo-144 boards untested.
2018-12-10 11:21:59 +00:00
#define IS_NUCLEO144 ( defined(ARDUINO_NUCLEO_F207ZG) \
|| defined(ARDUINO_NUCLEO_F429ZI) || defined(ARDUINO_NUCLEO_F767ZI) \
|| defined(ARDUINO_NUCLEO_L496ZG) || defined(ARDUINO_NUCLEO_L496ZG_P) \
add STM32H743 timing untested
2019-05-12 13:00:15 +01:00
|| defined(ARDUINO_NUCLEO_H743ZI) \
add Nucleo-144 boards, only F767ZI
2018-12-10 10:28:21 +00:00
)
rearrange STM32 shield macros
2018-01-27 00:12:01 +00:00
// F1xx, F4xx, L4xx have different registers and styles. General Macros
#if defined(__STM32F1__) //weird Maple Core
#define REGS(x) regs->x
#else //regular ST Core
add NUCLEO-L476 shield
2017-04-19 22:19:38 +01:00
#define REGS(x) x
add NUCLEO_F401RE, NUCLEO_F411RE
2018-01-26 22:02:58 +00:00
#endif
rearrange STM32 shield macros
2018-01-27 00:12:01 +00:00
#define PIN_HIGH(port, pin) (port)-> REGS(BSRR) = (1<<(pin))
#define PIN_LOW(port, pin) (port)-> REGS(BSRR) = (1<<((pin)+16))
#define PIN_MODE2(reg, pin, mode) reg=(reg&~(0x3<<((pin)<<1)))|(mode<<((pin)<<1))
#define GROUP_MODE(port, reg, mask, val) {port->REGS(reg) = (port->REGS(reg) & ~(mask)) | ((mask)&(val)); }
// Family specific Macros. F103 needs ST and Maple compatibility
adjust delays for F401, F411
2018-04-29 13:59:38 +01:00
// note that ILI9320 class of controller has much slower Read cycles
rearrange STM32 shield macros
2018-01-27 00:12:01 +00:00
#if 0
STM32 Core use ARDUINO_BLUEPILL_F103CB symbol
2020-06-08 08:48:39 +01:00
#elif defined(__STM32F1__) || defined(ARDUINO_BLUEPILL_F103C8) || defined(ARDUINO_BLUEPILL_F103CB) || defined(ARDUINO_NUCLEO_F103RB)
rearrange STM32 shield macros
2018-01-27 00:12:01 +00:00
#define WRITE_DELAY { }
STM32 Core use ARDUINO_BLUEPILL_F103CB symbol
2020-06-08 08:48:39 +01:00
#define READ_DELAY { RD_ACTIVE4; }
rearrange STM32 shield macros
2018-01-27 00:12:01 +00:00
#if defined(__STM32F1__) //MapleCore crts.o does RCC. not understand regular syntax anyway
#define GPIO_INIT()
#else
tidy up STM32F103, conditional GPIO_INIT macro
2017-03-27 16:38:55 +01:00
#define GPIO_INIT() { RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | RCC_APB2ENR_AFIOEN; \
AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_1;}
#endif
add STM32 IteadMaple Shield
2017-01-11 00:24:52 +00:00
#define GP_OUT(port, reg, mask) GROUP_MODE(port, reg, mask, 0x33333333)
#define GP_INP(port, reg, mask) GROUP_MODE(port, reg, mask, 0x44444444)
tidy up STM32F103, conditional GPIO_INIT macro
2017-03-27 16:38:55 +01:00
#define PIN_OUTPUT(port, pin) {\
stop left-shift warnings
2020-06-08 11:03:49 +01:00
if (pin < 8) {GP_OUT(port, CRL, 0xF<<((pin&7)<<2));} \
tidy up STM32F103, conditional GPIO_INIT macro
2017-03-27 16:38:55 +01:00
else {GP_OUT(port, CRH, 0xF<<((pin&7)<<2));} \
}
#define PIN_INPUT(port, pin) { \
stop left-shift warnings
2020-06-08 11:03:49 +01:00
if (pin < 8) { GP_INP(port, CRL, 0xF<<((pin&7)<<2)); } \
tidy up STM32F103, conditional GPIO_INIT macro
2017-03-27 16:38:55 +01:00
else { GP_INP(port, CRH, 0xF<<((pin&7)<<2)); } \
}
rearrange STM32 shield macros
2018-01-27 00:12:01 +00:00
// should be easy to add F030, F091, F303, L053, ...
nucleo64 shields
2018-04-22 21:04:56 +01:00
#elif defined(STM32F030x8)
#define WRITE_DELAY { }
#define READ_DELAY { RD_ACTIVE; }
#define GPIO_INIT() { RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN; }
rearrange STM32 shield macros
2018-01-27 00:12:01 +00:00
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
support NUCLEO-F072RB
2019-03-24 23:53:16 +00:00
#elif defined(STM32F072xB)
#define WRITE_DELAY { }
#define READ_DELAY { RD_ACTIVE; }
#define GPIO_INIT() { RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN; }
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
nucleo64 shields
2018-04-22 21:04:56 +01:00
#elif defined(STM32F091xC)
#define WRITE_DELAY { }
#define READ_DELAY { RD_ACTIVE; }
#define GPIO_INIT() { RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN; }
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
added more Nucleo-144 boards untested.
2018-12-10 11:21:59 +00:00
#elif defined(STM32F207xx)
#warning DELAY macros untested yet
#define WRITE_DELAY { WR_ACTIVE8; } //120MHz
#define IDLE_DELAY { WR_IDLE2;WR_IDLE; }
#define READ_DELAY { RD_ACTIVE16;}
Init all the GPIO ports. Adjust read timing.
2018-12-12 21:20:32 +00:00
#define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN; }
added more Nucleo-144 boards untested.
2018-12-10 11:21:59 +00:00
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
nucleo64 shields
2018-04-22 21:04:56 +01:00
#elif defined(STM32F303xE)
#define WRITE_DELAY { }
correct STM32F303 macros
2019-02-09 23:53:42 +00:00
#define READ_DELAY { RD_ACTIVE8; } //thanks MasterT
nucleo64 shields
2018-04-22 21:04:56 +01:00
#define GPIO_INIT() { RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN; \
/* AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_1; */ }
correct STM32F303 macros
2019-02-09 23:53:42 +00:00
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) //thanks fpiSTM
nucleo64 shields
2018-04-22 21:04:56 +01:00
adjust delays for F401, F411
2018-04-29 13:59:38 +01:00
#elif defined(STM32F401xE)
added more Nucleo-144 boards untested.
2018-12-10 11:21:59 +00:00
#define WRITE_DELAY { WR_ACTIVE2; } //84MHz
simplify XX_DELAY macros
2018-06-08 20:56:31 +01:00
#define READ_DELAY { RD_ACTIVE4; }
adjust delays for F401, F411
2018-04-29 13:59:38 +01:00
#define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN; }
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
#elif defined(STM32F411xE)
added more Nucleo-144 boards untested.
2018-12-10 11:21:59 +00:00
#define WRITE_DELAY { WR_ACTIVE2; WR_ACTIVE; } //100MHz
simplify XX_DELAY macros
2018-06-08 20:56:31 +01:00
#define READ_DELAY { RD_ACTIVE4; RD_ACTIVE2; }
rearrange STM32 shield macros
2018-01-27 00:12:01 +00:00
#define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN; }
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
added more Nucleo-144 boards untested.
2018-12-10 11:21:59 +00:00
#elif defined(STM32F429xx)
#warning DELAY macros untested yet
#define WRITE_DELAY { WR_ACTIVE8; } //180MHz
#define IDLE_DELAY { WR_IDLE2;WR_IDLE; }
#define READ_DELAY { RD_ACTIVE16;}
Init all the GPIO ports. Adjust read timing.
2018-12-12 21:20:32 +00:00
#define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN; }
added more Nucleo-144 boards untested.
2018-12-10 11:21:59 +00:00
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
add L152, F446
2018-05-14 22:56:32 +01:00
#elif defined(STM32F446xx)
add Nucleo-144 boards, only F767ZI
2018-12-10 10:28:21 +00:00
#define WRITE_DELAY { WR_ACTIVE8; } //180MHz
rearrange Due timing macros. add extra WR_IDLE for Due
2018-10-09 10:36:37 +01:00
#define IDLE_DELAY { WR_IDLE2;WR_IDLE; }
simplify XX_DELAY macros
2018-06-08 20:56:31 +01:00
#define READ_DELAY { RD_ACTIVE16;}
add L152, F446
2018-05-14 22:56:32 +01:00
#define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN; }
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
add Nucleo-144 boards, only F767ZI
2018-12-10 10:28:21 +00:00
#elif defined(STM32F767xx)
added more Nucleo-144 boards untested.
2018-12-10 11:21:59 +00:00
#warning DELAY macros untested yet
Init all the GPIO ports. Adjust read timing.
2018-12-12 21:20:32 +00:00
#define WRITE_DELAY { WR_ACTIVE8;WR_ACTIVE2; } //216MHz
#define IDLE_DELAY { WR_IDLE2;WR_IDLE; }
#define READ_DELAY { RD_ACTIVE16;RD_ACTIVE16;RD_ACTIVE4;}
#define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN; }
add Nucleo-144 boards, only F767ZI
2018-12-10 10:28:21 +00:00
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
add STM32H743 timing untested
2019-05-12 13:00:15 +01:00
#elif defined(STM32H743xx) // thanks MagicianT
#warning STM32H743xx< DELAY macros untested yet
#define WRITE_DELAY { WR_ACTIVE8;WR_ACTIVE2; } //F_CPU=400MHz
#define IDLE_DELAY { WR_IDLE2;WR_IDLE; }
#define READ_DELAY { RD_ACTIVE16;RD_ACTIVE16;RD_ACTIVE4;}
#define GPIO_INIT() { RCC->AHB4ENR |= RCC_AHB4ENR_GPIOAEN | RCC_AHB4ENR_GPIOCEN | RCC_AHB4ENR_GPIODEN | RCC_AHB4ENR_GPIOEEN | RCC_AHB4ENR_GPIOFEN; }
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
nucleo64 shields
2018-04-22 21:04:56 +01:00
#elif defined(STM32L053xx)
L152 is 32MHz M3
2019-09-11 10:01:51 +01:00
#define WRITE_DELAY { } //32MHz M0+
nucleo64 shields
2018-04-22 21:04:56 +01:00
#define READ_DELAY { RD_ACTIVE; }
#define GPIO_INIT() { RCC->IOPENR |= RCC_IOPENR_GPIOAEN | RCC_IOPENR_GPIOBEN | RCC_IOPENR_GPIOCEN; }
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
add L152, F446
2018-05-14 22:56:32 +01:00
#elif defined(STM32L152xE)
L152 is 32MHz M3
2019-09-11 10:01:51 +01:00
#define WRITE_DELAY { } //32MHz M3
add L152, F446
2018-05-14 22:56:32 +01:00
#define READ_DELAY { RD_ACTIVE; }
#define GPIO_INIT() { RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN; }
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
nucleo64 shields
2018-04-22 21:04:56 +01:00
#elif defined(STM32L476xx)
added more Nucleo-144 boards untested.
2018-12-10 11:21:59 +00:00
#define WRITE_DELAY { WR_ACTIVE2; } //80MHz
simplify XX_DELAY macros
2018-06-08 20:56:31 +01:00
#define READ_DELAY { RD_ACTIVE4; RD_ACTIVE; }
nucleo64 shields
2018-04-22 21:04:56 +01:00
#define GPIO_INIT() { RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOBEN | RCC_AHB2ENR_GPIOCEN; }
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
added more Nucleo-144 boards untested.
2018-12-10 11:21:59 +00:00
#elif defined(STM32L496xx)
#warning DELAY macros untested yet
#define WRITE_DELAY { WR_ACTIVE2; } //80MHz
simplify XX_DELAY macros
2018-06-08 20:56:31 +01:00
#define READ_DELAY { RD_ACTIVE4; RD_ACTIVE; }
Init all the GPIO ports. Adjust read timing.
2018-12-12 21:20:32 +00:00
#define GPIO_INIT() { RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOCEN | RCC_AHB2ENR_GPIODEN | RCC_AHB2ENR_GPIOEEN | RCC_AHB2ENR_GPIOFEN; }
nucleo64 shields
2018-04-22 21:04:56 +01:00
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
rearrange STM32 shield macros
2018-01-27 00:12:01 +00:00
#else
#error unsupported STM32
add NUCLEO-L476 shield
2017-04-19 22:19:38 +01:00
#endif
add STM32 IteadMaple Shield
2017-01-11 00:24:52 +00:00
add MY_BLUEPILL adapter
2017-03-31 20:50:37 +01:00
#if 0
STM32 Core use ARDUINO_BLUEPILL_F103CB symbol
2020-06-08 08:48:39 +01:00
#elif defined(ARDUINO_GENERIC_STM32F103C) || defined(ARDUINO_BLUEPILL_F103C8) || defined(ARDUINO_BLUEPILL_F103CB)
tidy up STM32F103, conditional GPIO_INIT macro
2017-03-27 16:38:55 +01:00
#warning Uno Shield on BLUEPILL
Add standard wiring info
2019-03-26 12:40:04 +00:00
add BLUEPILL Adapter Shield wiring
2019-03-27 16:43:45 +00:00
//LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST| |SD_SS|SD_DI|SD_DO|SD_SCK|
corrected the BLUEPILL Adapter SPI pins
2019-03-28 14:24:34 +00:00
//STM32 pin |PA7|PA6|PA5|PA4|PA3|PA2|PA1|PA0| |PB0|PB6|PB7|PB8|PB9| |PA15 |PB5 |PB4 |PB3 | **ALT-SPI1**
Add standard wiring info
2019-03-26 12:40:04 +00:00
tidy up STM32F103, conditional GPIO_INIT macro
2017-03-27 16:38:55 +01:00
#define RD_PORT GPIOB
new ST Core supports BluePill
2018-04-28 10:33:26 +01:00
//#define RD_PIN 5
#define RD_PIN 0 //hardware mod to Adapter. Allows use of PB5 for SD Card
tidy up STM32F103, conditional GPIO_INIT macro
2017-03-27 16:38:55 +01:00
#define WR_PORT GPIOB
#define WR_PIN 6
#define CD_PORT GPIOB
#define CD_PIN 7
#define CS_PORT GPIOB
#define CS_PIN 8
#define RESET_PORT GPIOB
#define RESET_PIN 9
// configure macros for the data pins
#define write_8(d) { GPIOA->REGS(BSRR) = 0x00FF << 16; GPIOA->REGS(BSRR) = (d) & 0xFF; }
#define read_8() (GPIOA->REGS(IDR) & 0xFF)
// PA7 ..PA0
#define setWriteDir() {GP_OUT(GPIOA, CRL, 0xFFFFFFFF); }
#define setReadDir() {GP_INP(GPIOA, CRL, 0xFFFFFFFF); }
add Nucleo-144 boards, only F767ZI
2018-12-10 10:28:21 +00:00
#elif IS_NUCLEO64 // Uno Shield on NUCLEO-64
#warning Uno Shield on NUCLEO-64
cosmetic comments
2018-12-11 12:26:22 +00:00
#define RD_PORT GPIOA //PA0
add write delay for ZERO, add macros for NUCLEO-STM32F103
2016-11-15 11:49:56 +00:00
#define RD_PIN 0
cosmetic comments
2018-12-11 12:26:22 +00:00
#define WR_PORT GPIOA //PA1
add write delay for ZERO, add macros for NUCLEO-STM32F103
2016-11-15 11:49:56 +00:00
#define WR_PIN 1
cosmetic comments
2018-12-11 12:26:22 +00:00
#define CD_PORT GPIOA //PA4
add write delay for ZERO, add macros for NUCLEO-STM32F103
2016-11-15 11:49:56 +00:00
#define CD_PIN 4
cosmetic comments
2018-12-11 12:26:22 +00:00
#define CS_PORT GPIOB //PB0
add write delay for ZERO, add macros for NUCLEO-STM32F103
2016-11-15 11:49:56 +00:00
#define CS_PIN 0
cosmetic comments
2018-12-11 12:26:22 +00:00
#define RESET_PORT GPIOC //PC1
add write delay for ZERO, add macros for NUCLEO-STM32F103
2016-11-15 11:49:56 +00:00
#define RESET_PIN 1
// configure macros for the data pins
cosmetic comments
2018-12-11 12:26:22 +00:00
#define AMASK ((1<<9)|(1<<10)|(1<<8)) //#0, #2, #7
#define BMASK ((1<<3)|(1<<5)|(1<<4)|(1<<10)) //#3, #4, #5, #6
#define CMASK ((1<<7)) //#1
tidy up STM32F103, conditional GPIO_INIT macro
2017-03-27 16:38:55 +01:00
#define write_8(d) { \
cosmetic comments
2018-12-11 12:26:22 +00:00
GPIOA->REGS(BSRR) = AMASK << 16; \
GPIOB->REGS(BSRR) = BMASK << 16; \
GPIOC->REGS(BSRR) = CMASK << 16; \
tidy up STM32F103, conditional GPIO_INIT macro
2017-03-27 16:38:55 +01:00
GPIOA->REGS(BSRR) = ( ((d) & (1<<0)) << 9) \
| (((d) & (1<<2)) << 8) \
| (((d) & (1<<7)) << 1); \
GPIOB->REGS(BSRR) = ( ((d) & (1<<3)) << 0) \
| (((d) & (1<<4)) << 1) \
| (((d) & (1<<5)) >> 1) \
| (((d) & (1<<6)) << 4); \
GPIOC->REGS(BSRR) = ( ((d) & (1<<1)) << 6); \
add write delay for ZERO, add macros for NUCLEO-STM32F103
2016-11-15 11:49:56 +00:00
}
tidy up STM32F103, conditional GPIO_INIT macro
2017-03-27 16:38:55 +01:00
#define read_8() ( ( ( (GPIOA->REGS(IDR) & (1<<9)) >> 9) \
| ((GPIOC->REGS(IDR) & (1<<7)) >> 6) \
| ((GPIOA->REGS(IDR) & (1<<10)) >> 8) \
| ((GPIOB->REGS(IDR) & (1<<3)) >> 0) \
| ((GPIOB->REGS(IDR) & (1<<5)) >> 1) \
| ((GPIOB->REGS(IDR) & (1<<4)) << 1) \
| ((GPIOB->REGS(IDR) & (1<<10)) >> 4) \
| ((GPIOA->REGS(IDR) & (1<<8)) >> 1)))
add write delay for ZERO, add macros for NUCLEO-STM32F103
2016-11-15 11:49:56 +00:00
add NUCLEO-L476 shield
2017-04-19 22:19:38 +01:00
rearrange STM32 shield macros
2018-01-27 00:12:01 +00:00
#if defined(ARDUINO_NUCLEO_F103RB) || defined(ARDUINO_STM_NUCLEO_F103RB) //F103 has unusual GPIO modes
// PA10,PA9,PA8 PB10 PB5,PB4,PB3 PC7
#define setWriteDir() {GP_OUT(GPIOA, CRH, 0xFFF); GP_OUT(GPIOB, CRH, 0xF00); GP_OUT(GPIOB, CRL, 0xFFF000); GP_OUT(GPIOC, CRL, 0xF0000000); }
#define setReadDir() {GP_INP(GPIOA, CRH, 0xFFF); GP_INP(GPIOB, CRH, 0xF00); GP_INP(GPIOB, CRL, 0xFFF000); GP_INP(GPIOC, CRL, 0xF0000000); }
#else //F0xx, F3xx, F4xx, L0xx, L1xx, L4xx use MODER
add NUCLEO-L476 shield
2017-04-19 22:19:38 +01:00
// PA10,PA9,PA8 PB10,PB5,PB4,PB3 PC7
#define setWriteDir() { setReadDir(); \
GPIOA->MODER |= 0x150000; GPIOB->MODER |= 0x100540; GPIOC->MODER |= 0x4000; }
#define setReadDir() { GPIOA->MODER &= ~0x3F0000; GPIOB->MODER &= ~0x300FC0; GPIOC->MODER &= ~0xC000; }
#endif
add write delay for ZERO, add macros for NUCLEO-STM32F103
2016-11-15 11:49:56 +00:00
add Nucleo-144 boards, only F767ZI
2018-12-10 10:28:21 +00:00
#elif IS_NUCLEO144 // Uno Shield on NUCLEO-144
#warning Uno Shield on NUCLEO-144
cosmetic comments
2018-12-11 12:26:22 +00:00
#define RD_PORT GPIOA //PA3
add Nucleo-144 boards, only F767ZI
2018-12-10 10:28:21 +00:00
#define RD_PIN 3
cosmetic comments
2018-12-11 12:26:22 +00:00
#define WR_PORT GPIOC //PC0
add Nucleo-144 boards, only F767ZI
2018-12-10 10:28:21 +00:00
#define WR_PIN 0
cosmetic comments
2018-12-11 12:26:22 +00:00
#define CD_PORT GPIOC //PC3
add Nucleo-144 boards, only F767ZI
2018-12-10 10:28:21 +00:00
#define CD_PIN 3
cosmetic comments
2018-12-11 12:26:22 +00:00
#define CS_PORT GPIOF //PF3
add Nucleo-144 boards, only F767ZI
2018-12-10 10:28:21 +00:00
#define CS_PIN 3
cosmetic comments
2018-12-11 12:26:22 +00:00
#define RESET_PORT GPIOF //PF5
add Nucleo-144 boards, only F767ZI
2018-12-10 10:28:21 +00:00
#define RESET_PIN 5
// configure macros for the data pins
corrected my macros -- I hope
2018-12-10 22:45:23 +00:00
#define DMASK ((1<<15)) //#1
#define EMASK ((1<<13)|(1<<11)|(1<<9)) //#3, #5, #6
#define FMASK ((1<<12)|(1<<15)|(1<<14)|(1<<13)) //#0, #2, #4, #7
add Nucleo-144 boards, only F767ZI
2018-12-10 10:28:21 +00:00
#define write_8(d) { \
GPIOD->REGS(BSRR) = DMASK << 16; \
GPIOE->REGS(BSRR) = EMASK << 16; \
GPIOF->REGS(BSRR) = FMASK << 16; \
GPIOD->REGS(BSRR) = ( ((d) & (1<<1)) << 14); \
GPIOE->REGS(BSRR) = ( ((d) & (1<<3)) << 10) \
| (((d) & (1<<5)) << 6) \
| (((d) & (1<<6)) << 3); \
GPIOF->REGS(BSRR) = ( ((d) & (1<<0)) << 12) \
| (((d) & (1<<2)) << 13) \
| (((d) & (1<<4)) << 10) \
| (((d) & (1<<7)) << 6); \
}
#define read_8() ( ( ( (GPIOF->REGS(IDR) & (1<<12)) >> 12) \
| ((GPIOD->REGS(IDR) & (1<<15)) >> 14) \
| ((GPIOF->REGS(IDR) & (1<<15)) >> 13) \
| ((GPIOE->REGS(IDR) & (1<<13)) >> 10) \
| ((GPIOF->REGS(IDR) & (1<<14)) >> 10) \
| ((GPIOE->REGS(IDR) & (1<<11)) >> 6) \
| ((GPIOE->REGS(IDR) & (1<<9)) >> 3) \
| ((GPIOF->REGS(IDR) & (1<<13)) >> 6)))
corrected my macros -- I hope
2018-12-10 22:45:23 +00:00
// PD15 PE13,PE11,PE9 PF15,PF14,PF13,PF12
add Nucleo-144 boards, only F767ZI
2018-12-10 10:28:21 +00:00
#define setWriteDir() { setReadDir(); \
corrected my macros -- I hope
2018-12-10 22:45:23 +00:00
GPIOD->MODER |= 0x40000000; GPIOE->MODER |= 0x04440000; GPIOF->MODER |= 0x55000000; }
#define setReadDir() { GPIOD->MODER &= ~0xC0000000; GPIOE->MODER &= ~0x0CCC0000; GPIOF->MODER &= ~0xFF000000; }
add Nucleo-144 boards, only F767ZI
2018-12-10 10:28:21 +00:00
tidy up STM32F103, conditional GPIO_INIT macro
2017-03-27 16:38:55 +01:00
#elif defined(ARDUINO_MAPLE_REV3) // Uno Shield on MAPLE_REV3 board
add STM32 IteadMaple Shield
2017-01-11 00:24:52 +00:00
#warning Uno Shield on MAPLE_REV3 board
#define RD_PORT GPIOC
#define RD_PIN 0
#define WR_PORT GPIOC
#define WR_PIN 1
#define CD_PORT GPIOC
#define CD_PIN 2
#define CS_PORT GPIOC
#define CS_PIN 3
#define RESET_PORT GPIOC
#define RESET_PIN 4
// configure macros for the data pins
tidy up STM32F103, conditional GPIO_INIT macro
2017-03-27 16:38:55 +01:00
#define write_8(d) { \
GPIOA->REGS(BSRR) = 0x0703 << 16; \
GPIOB->REGS(BSRR) = 0x00E0 << 16; \
GPIOA->REGS(BSRR) = ( ((d) & (1<<0)) << 10) \
| (((d) & (1<<2)) >> 2) \
| (((d) & (1<<3)) >> 2) \
| (((d) & (1<<6)) << 2) \
| (((d) & (1<<7)) << 2); \
GPIOB->REGS(BSRR) = ( ((d) & (1<<1)) << 6) \
| (((d) & (1<<4)) << 1) \
| (((d) & (1<<5)) << 1); \
add STM32 IteadMaple Shield
2017-01-11 00:24:52 +00:00
}
tidy up STM32F103, conditional GPIO_INIT macro
2017-03-27 16:38:55 +01:00
#define read_8() ( ( ( (GPIOA->REGS(IDR) & (1<<10)) >> 10) \
| ((GPIOB->REGS(IDR) & (1<<7)) >> 6) \
| ((GPIOA->REGS(IDR) & (1<<0)) << 2) \
| ((GPIOA->REGS(IDR) & (1<<1)) << 2) \
| ((GPIOB->REGS(IDR) & (1<<5)) >> 1) \
| ((GPIOB->REGS(IDR) & (1<<6)) >> 1) \
| ((GPIOA->REGS(IDR) & (1<<8)) >> 2) \
| ((GPIOA->REGS(IDR) & (1<<9)) >> 2)))
add STM32 IteadMaple Shield
2017-01-11 00:24:52 +00:00
// PA10,PA9,PA8 PA1,PA0 PB7,PB6,PB5
#define setWriteDir() {GP_OUT(GPIOA, CRH, 0xFFF); GP_OUT(GPIOA, CRL, 0xFF); GP_OUT(GPIOB, CRL, 0xFFF00000); }
#define setReadDir() {GP_INP(GPIOA, CRH, 0xFFF); GP_INP(GPIOA, CRL, 0xFF); GP_INP(GPIOB, CRL, 0xFFF00000); }
tidy up STM32F103, conditional GPIO_INIT macro
2017-03-27 16:38:55 +01:00
#else
#error REGS group
#endif
add driver for BluePill Shield Adapter
2017-03-22 22:35:26 +00:00
WR_IDLE macros
2018-07-17 09:54:50 +01:00
#ifndef IDLE_DELAY
#define IDLE_DELAY { WR_IDLE; }
#endif
#define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; IDLE_DELAY; }
add driver for BluePill Shield Adapter
2017-03-22 22:35:26 +00:00
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
Init all the GPIO ports. Adjust read timing.
2018-12-12 21:20:32 +00:00
#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE2; RD_IDLE; }
add driver for BluePill Shield Adapter
2017-03-22 22:35:26 +00:00
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
add driver for mega1284P Bobuino
2017-12-31 21:16:48 +00:00
//################################### ESP32 ##############################
add TTGO D1 R32 (ESP32 shield). note you must hard-wire 3 control pins
2017-09-17 11:37:08 +01:00
#elif defined(ESP32) //regular UNO shield on TTGO D1 R32 (ESP32)
#define LCD_RD 2 //LED
#define LCD_WR 4
#define LCD_RS 15 //hard-wired to A2 (GPIO35)
#define LCD_CS 33 //hard-wired to A3 (GPIO34)
#define LCD_RST 32 //hard-wired to A4 (GPIO36)
#define LCD_D0 12
#define LCD_D1 13
#define LCD_D2 26
#define LCD_D3 25
#define LCD_D4 17
#define LCD_D5 16
#define LCD_D6 27
#define LCD_D7 14
add (unused) ESP32 port register names
2017-09-17 23:14:49 +01:00
#define RD_PORT GPIO.out
add TTGO D1 R32 (ESP32 shield). note you must hard-wire 3 control pins
2017-09-17 11:37:08 +01:00
#define RD_PIN LCD_RD
add (unused) ESP32 port register names
2017-09-17 23:14:49 +01:00
#define WR_PORT GPIO.out
add TTGO D1 R32 (ESP32 shield). note you must hard-wire 3 control pins
2017-09-17 11:37:08 +01:00
#define WR_PIN LCD_WR
add (unused) ESP32 port register names
2017-09-17 23:14:49 +01:00
#define CD_PORT GPIO.out
add TTGO D1 R32 (ESP32 shield). note you must hard-wire 3 control pins
2017-09-17 11:37:08 +01:00
#define CD_PIN LCD_RS
add (unused) ESP32 port register names
2017-09-17 23:14:49 +01:00
#define CS_PORT GPIO.out1.val
add TTGO D1 R32 (ESP32 shield). note you must hard-wire 3 control pins
2017-09-17 11:37:08 +01:00
#define CS_PIN LCD_CS
add (unused) ESP32 port register names
2017-09-17 23:14:49 +01:00
#define RESET_PORT GPIO.out1.val
add TTGO D1 R32 (ESP32 shield). note you must hard-wire 3 control pins
2017-09-17 11:37:08 +01:00
#define RESET_PIN LCD_RST
static inline uint32_t map_8(uint32_t d)
{
return (
0
| ((d & (1 << 0)) << (LCD_D0 - 0))
| ((d & (1 << 1)) << (LCD_D1 - 1))
| ((d & (1 << 2)) << (LCD_D2 - 2))
| ((d & (1 << 3)) << (LCD_D3 - 3))
| ((d & (1 << 4)) << (LCD_D4 - 4))
| ((d & (1 << 5)) << (LCD_D5 - 5))
| ((d & (1 << 6)) << (LCD_D6 - 6))
| ((d & (1 << 7)) << (LCD_D7 - 7))
);
}
static inline uint8_t map_32(uint32_t d)
{
return (
0
| ((d & (1 << LCD_D0)) >> (LCD_D0 - 0))
| ((d & (1 << LCD_D1)) >> (LCD_D1 - 1))
| ((d & (1 << LCD_D2)) >> (LCD_D2 - 2))
| ((d & (1 << LCD_D3)) >> (LCD_D3 - 3))
| ((d & (1 << LCD_D4)) >> (LCD_D4 - 4))
| ((d & (1 << LCD_D5)) >> (LCD_D5 - 5))
| ((d & (1 << LCD_D6)) >> (LCD_D6 - 6))
| ((d & (1 << LCD_D7)) >> (LCD_D7 - 7))
);
}
static inline void write_8(uint16_t data)
{
GPIO.out_w1tc = map_8(0xFF); //could define once as DMASK
GPIO.out_w1ts = map_8(data);
}
static inline uint8_t read_8()
{
return map_32(GPIO.in);
}
static void setWriteDir()
{
pinMode(LCD_D0, OUTPUT);
pinMode(LCD_D1, OUTPUT);
pinMode(LCD_D2, OUTPUT);
pinMode(LCD_D3, OUTPUT);
pinMode(LCD_D4, OUTPUT);
pinMode(LCD_D5, OUTPUT);
pinMode(LCD_D6, OUTPUT);
pinMode(LCD_D7, OUTPUT);
}
static void setReadDir()
{
pinMode(LCD_D0, INPUT);
pinMode(LCD_D1, INPUT);
pinMode(LCD_D2, INPUT);
pinMode(LCD_D3, INPUT);
pinMode(LCD_D4, INPUT);
pinMode(LCD_D5, INPUT);
pinMode(LCD_D6, INPUT);
pinMode(LCD_D7, INPUT);
}
#define WRITE_DELAY { }
#define READ_DELAY { }
#define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; }
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; }
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
#define PIN_LOW(p, b) (digitalWrite(b, LOW))
#define PIN_HIGH(p, b) (digitalWrite(b, HIGH))
#define PIN_OUTPUT(p, b) (pinMode(b, OUTPUT))
support NANO33_BLE
2021-01-20 15:49:09 +00:00
//################################## NANO33 BLE ############################
#elif defined(ARDUINO_ARDUINO_NANO33BLE)
#warning regular UNO shield on a Nano33 BLE
//LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST |
//BLE pin |P0.23|P1.14|P1.13|P1.15|P1.12|P1.11|P0.27|P0.21| |P0.4|P0.5|P0.30|P0.29|P0.31|
add Nano pins for ARDUINO_ARDUINO_NANO33BLE
2021-02-23 10:03:33 +00:00
//NANO pins |7 |6 |5 |4 |3 |2 |9 |8 | |A0 |A1 |A2 |A3 |A4 |
support NANO33_BLE
2021-01-20 15:49:09 +00:00
#define WRITE_DELAY { WR_ACTIVE8; } //M4F @ 64MHz
#define IDLE_DELAY { WR_IDLE2; }
#define READ_DELAY { RD_ACTIVE4; RD_ACTIVE; }
#define RD_PORT NRF_P0
#define RD_PIN 4
#define WR_PORT NRF_P0
#define WR_PIN 5
#define CD_PORT NRF_P0
#define CD_PIN 30
#define CS_PORT NRF_P0
#define CS_PIN 29
#define RESET_PORT NRF_P0
#define RESET_PIN 31
// configure macros for the data pins
#define P0MASK ((1<<23)|(1<<27)|(1<<21)) //NRF_P0
#define P1MASK ((1<<14)|(1<<13)|(1<<15)|(1<<12)|(1<<11)) //NRF_P1
#define write_8(d) { \
NRF_P0->OUTCLR = P0MASK; NRF_P1->OUTCLR = P1MASK; \
NRF_P0->OUTSET = (((d) & (1 << 0)) << 21) \
| (((d) & (1 << 1)) << 26) \
| (((d) & (1 << 7)) << 16); \
NRF_P1->OUTSET = (((d) & (1 << 2)) << 9) \
| (((d) & (1 << 3)) << 9) \
| (((d) & (1 << 4)) << 11) \
| (((d) & (1 << 5)) << 8) \
| (((d) & (1 << 6)) << 8); \
}
#define read_8() ((((NRF_P0->IN & (1<<21)) >> 21) \
| ((NRF_P0->IN & (1 << 27)) >> 26) \
| ((NRF_P1->IN & (1 << 11)) >> 9) \
| ((NRF_P1->IN & (1 << 12)) >> 9) \
| ((NRF_P1->IN & (1 << 15)) >> 11) \
| ((NRF_P1->IN & (1 << 13)) >> 8) \
| ((NRF_P1->IN & (1 << 14)) >> 8) \
| ((NRF_P0->IN & (1 << 23)) >> 16)))
#define BUS_CNF(x) {\
NRF_P0->PIN_CNF[21] = x;\
NRF_P0->PIN_CNF[27] = x;\
NRF_P1->PIN_CNF[11] = x;\
NRF_P1->PIN_CNF[12] = x;\
NRF_P1->PIN_CNF[15] = x;\
NRF_P1->PIN_CNF[13] = x;\
NRF_P1->PIN_CNF[14] = x;\
NRF_P0->PIN_CNF[23] = x;\
}
#define setWriteDir() {BUS_CNF(3); }
#define setReadDir() {BUS_CNF(0); }
#define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; IDLE_DELAY; }
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; } //PJ adjusted
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
//#define GPIO_INIT() {for (int i = A0; i <= A4; i++) pinMode(i, OUTPUT);}
#define PIN_LOW(port, pin) (port)->OUTCLR = (1<<(pin))
#define PIN_HIGH(port, pin) (port)->OUTSET = (1<<(pin))
#define PIN_OUTPUT(port, pin) (port)->DIR |= (1<<(pin))
//############################# END OF BLOCKS ############################
start off commit
2016-03-15 21:03:51 +00:00
#else
#error MCU unsupported
#endif // regular UNO shields on Arduino boards
#endif //!defined(USE_SPECIAL) || defined (USE_SPECIAL_FAIL)
#define RD_ACTIVE PIN_LOW(RD_PORT, RD_PIN)
#define RD_IDLE PIN_HIGH(RD_PORT, RD_PIN)
#define RD_OUTPUT PIN_OUTPUT(RD_PORT, RD_PIN)
#define WR_ACTIVE PIN_LOW(WR_PORT, WR_PIN)
#define WR_IDLE PIN_HIGH(WR_PORT, WR_PIN)
#define WR_OUTPUT PIN_OUTPUT(WR_PORT, WR_PIN)
#define CD_COMMAND PIN_LOW(CD_PORT, CD_PIN)
#define CD_DATA PIN_HIGH(CD_PORT, CD_PIN)
#define CD_OUTPUT PIN_OUTPUT(CD_PORT, CD_PIN)
#define CS_ACTIVE PIN_LOW(CS_PORT, CS_PIN)
#define CS_IDLE PIN_HIGH(CS_PORT, CS_PIN)
#define CS_OUTPUT PIN_OUTPUT(CS_PORT, CS_PIN)
#define RESET_ACTIVE PIN_LOW(RESET_PORT, RESET_PIN)
#define RESET_IDLE PIN_HIGH(RESET_PORT, RESET_PIN)
#define RESET_OUTPUT PIN_OUTPUT(RESET_PORT, RESET_PIN)
// General macros. IOCLR registers are 1 cycle when optimised.
#define WR_STROBE { WR_ACTIVE; WR_IDLE; } //PWLW=TWRL=50ns
#define RD_STROBE RD_IDLE, RD_ACTIVE, RD_ACTIVE, RD_ACTIVE //PWLR=TRDL=150ns, tDDR=100ns
tidy up STM32F103, conditional GPIO_INIT macro
2017-03-27 16:38:55 +01:00
#if !defined(GPIO_INIT)
#define GPIO_INIT()
add delays for Teensy, kludge pinMode for Teensy
2016-09-27 12:06:03 +01:00
#endif
tidy up STM32F103, conditional GPIO_INIT macro
2017-03-27 16:38:55 +01:00
#define CTL_INIT() { GPIO_INIT(); RD_OUTPUT; WR_OUTPUT; CD_OUTPUT; CS_OUTPUT; RESET_OUTPUT; }
alter WriteCmd macro to CD_DATA at the end
2017-12-25 17:08:04 +00:00
#define WriteCmd(x) { CD_COMMAND; write16(x); CD_DATA; }
#define WriteData(x) { write16(x); }
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