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https://github.com/YuzuZensai/MCUFRIEND_kbv.git
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Test 7793 (#206)
* add USE_MKR2UNO block. UNTESTED * add MKR2UNO pins for SD * WRITE_DELAY macros for MEGA2560 shields * add CURIOSITY_AVR128 protoShields, add XPRO-4809 wiring * update Curiosity, Xmrga pins * COOCOX_STM32 * append Curiosity pinout. remove USE_COOCOX_STM32, USE_MKR2UNO.specials * append untested USE_COOCOX_STM32, USE_MKR2UNO.specials * default
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prenticedavid
@@ -1789,4 +1789,127 @@ static void setReadDir()
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#define PIN_HIGH(p, b) (digitalWrite(b, HIGH))
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#define PIN_OUTPUT(p, b) (pinMode(b, OUTPUT))
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//#### UNTESTED ############### COOCOX_STM32 on STM32103RB ##############################
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//#define USE_COOCOX_STM32
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#elif defined(USE_COOCOX_STM32) && (defined(ARDUINO_GENERIC_STM32F103R)||defined(ARDUINO_GENERIC_F103RBTX))
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#warning Uno Shield on USE_COOCOX_STM32
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//LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST| |SD_SS|SD_DI|SD_DO|SD_SCK| |SDA|SCL|
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//STM32 pin |PD2|PC9|PC8|PC7|PC6|PC12|PA8|PA15| |PC0|PC1|PC2|PC3|PB7| |PB12 |PB15 |PB14 |PB13 | |PB7|PB6|
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#if defined(ARDUINO_GENERIC_F103RBTX) //regular CMSIS libraries
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#define REGS(x) x
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#define GPIO_INIT() { RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | RCC_APB2ENR_AFIOEN; \
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AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_1;}
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#else //weird Maple libraries
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#define REGS(x) regs->x
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#endif
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#define WRITE_DELAY { }
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#define READ_DELAY { RD_ACTIVE4; }
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#define GROUP_MODE(port, reg, mask, val) {port->REGS(reg) = (port->REGS(reg) & ~(mask)) | ((mask)&(val)); }
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#define GP_OUT(port, reg, mask) GROUP_MODE(port, reg, mask, 0x33333333)
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#define GP_INP(port, reg, mask) GROUP_MODE(port, reg, mask, 0x44444444)
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#define PIN_OUTPUT(port, pin) {\
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if (pin < 8) {GP_OUT(port, CRL, 0xF<<((pin)<<2));} \
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else {GP_OUT(port, CRH, 0xF<<((pin&7)<<2));} \
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}
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#define PIN_INPUT(port, pin) { \
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if (pin < 8) { GP_INP(port, CRL, 0xF<<((pin)<<2)); } \
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else { GP_INP(port, CRH, 0xF<<((pin&7)<<2)); } \
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}
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#define PIN_HIGH(port, pin) (port)-> REGS(BSRR) = (1<<(pin))
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#define PIN_LOW(port, pin) (port)-> REGS(BSRR) = (1<<((pin)+16))
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#define RD_PORT GPIOC
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#define RD_PIN 0
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#define WR_PORT GPIOC
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#define WR_PIN 1
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#define CD_PORT GPIOC
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#define CD_PIN 2
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#define CS_PORT GPIOC
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#define CS_PIN 3
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#define RESET_PORT GPIOB
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#define RESET_PIN 7
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// configure macros for the data pins
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#define AMASK ((1<<8)|(1<<15))
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#define CMASK ((15<<6)|(1<<12))
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#define DMASK (1<<2)
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#define write_8(d) { GPIOA->REGS(BSRR) = AMASK << 16; GPIOC->REGS(BSRR) = CMASK << 16;\
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GPIOD->REGS(BSRR) = DMASK << 16; \
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GPIOA->REGS(BSRR) = (((d) & (1<<0)) << 15); \
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GPIOA->REGS(BSRR) = (((d) & (1<<1)) << 4); \
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GPIOC->REGS(BSRR) = (((d) & (1<<2)) << 10); \
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GPIOC->REGS(BSRR) = (((d) &(15<<3)) << 3); \
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GPIOD->REGS(BSRR) = (((d) & (1<<7)) >> 5); \
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}
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#define read_8() ( ((GPIOA->REGS(IDR) & (1<<15)) >> 15) \
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| ((GPIOA->REGS(IDR) & (1<<8)) >> 7) \
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| ((GPIOC->REGS(IDR) & (1<<12)) >> 10) \
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| ((GPIOC->REGS(IDR) & (15<<6)) >> 3) \
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| ((GPIOD->REGS(IDR) & (1<<2)) << 5) \
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)
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// PA15,PA8 PC12,PC9-PC8 PC7,PC6 PD2
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#define setWriteDir() {GP_OUT(GPIOA, CRH, 0xF000000F); GP_OUT(GPIOC, CRH, 0xF00FF); GP_OUT(GPIOC, CRL, 0xFF000000); GP_OUT(GPIOD, CRL, 0xF00); }
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#define setReadDir() {GP_INP(GPIOA, CRH, 0xF000000F); GP_INP(GPIOC, CRH, 0xF00FF); GP_INP(GPIOC, CRL, 0xFF000000); GP_INP(GPIOD, CRL, 0xF00); }
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#define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; }
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#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
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#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; }
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#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
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//#### UNTESTED ############# MKR2UNO ############################
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//#define USE_MKR2UNO
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#elif defined(__SAMD21G18A__) && defined(USE_MKR2UNO) //regular UNO shield on MKE2UNO Adapter
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//LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST | |SDCS|SDDI|SDDO|SDSCK|
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//SAMD21 pin |PA21|PA20|PB11|PB10|PA11|PA10|PA17|PA16| |PA2|PB2|PB3 |PA4 |PA5 | |PA23|PA8 |PA9 |PA22 |
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//MKR2UNO pin|7 |6 |5 |4 |3 |2 |9 |8 | |A0 |A1 |A2 |A3 |A4 | |10 |11 |12 |13 |
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#include "sam.h"
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// configure macros for the control pins
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#define RD_PORT PORT->Group[0]
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#define RD_PIN 2
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#define WR_PORT PORT->Group[1]
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#define WR_PIN 2
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#define CD_PORT PORT->Group[1]
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#define CD_PIN 3
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#define CS_PORT PORT->Group[0]
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#define CS_PIN 4
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#define RESET_PORT PORT->Group[0]
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#define RESET_PIN 5
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// configure macros for data bus
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#define AMASK ((3<<20)|(3<<10)|(3<<16)) //|PA21|PA20|PA11|PA10|PA17|PA16|
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#define BMASK ((1<<11)|(1<<10)) //|PB11|PB10|
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#define WRMASK ((0<<22) | (1<<28) | (1<<30)) //
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#define RDMASK ((1<<17) | (1<<28) | (1<<30)) //
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#define write_8(x) {\
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PORT->Group[0].OUTCLR.reg = AMASK;PORT->Group[1].OUTCLR.reg = BMASK;\
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PORT->Group[0].OUTSET.reg = (((x) & (3<<0)) << 16)\
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|(((x) & (3<<2)) << 8)\
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|(((x) & (3<<6)) << 14);\
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PORT->Group[1].OUTSET.reg = (((x) & (3<<4)) << 6);\
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}
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#define read_8() (((PORT->Group[0].IN.reg >> 16) & (3<<0))\
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|((PORT->Group[0].IN.reg >> 8) & (3<<2))\
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|((PORT->Group[1].IN.reg >> 6) & (3<<4))\
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|((PORT->Group[0].IN.reg >> 14) & (3<<6)))
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#define setWriteDir() { PORT->Group[0].DIRSET.reg = AMASK;PORT->Group[0].DIRSET.reg = BMASK; \
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PORT->Group[0].WRCONFIG.reg = (AMASK & 0xFFFF) | WRMASK; \
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PORT->Group[1].WRCONFIG.reg = (BMASK & 0xFFFF) | WRMASK; \
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PORT->Group[0].WRCONFIG.reg = (AMASK>>16) | WRMASK | (1<<31); \
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}
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#define setReadDir() { PORT->Group[0].DIRCLR.reg = AMASK;PORT->Group[1].DIRCLR.reg = BMASK; \
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PORT->Group[0].WRCONFIG.reg = (AMASK & 0xFFFF) | RDMASK; \
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PORT->Group[1].WRCONFIG.reg = (BMASK & 0xFFFF) | RDMASK; \
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PORT->Group[0].WRCONFIG.reg = (AMASK>>16) | RDMASK | (1<<31); \
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}
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#define write8(x) { write_8(x); WR_ACTIVE; WR_STROBE; }
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#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
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#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
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#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
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// Shield Control macros.
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#define PIN_LOW(port, pin) (port).OUTCLR.reg = (1<<(pin))
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#define PIN_HIGH(port, pin) (port).OUTSET.reg = (1<<(pin))
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#define PIN_OUTPUT(port, pin) (port).DIR.reg |= (1<<(pin))
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// ######################### ###################
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