From 9564ca51129591440023f77325d7fc26f67899a0 Mon Sep 17 00:00:00 2001
From: prenticedavid <david.prentice@farming.co.uk>
Date: Sun, 30 Jun 2019 10:07:42 +0100
Subject: [PATCH] add WR_ACTIVEn macros.  conditional delays for STM32 targets

---
 utility/mcufriend_keil.h | 49 ++++++++++++++++++++++++++++++++++++----
 1 file changed, 45 insertions(+), 4 deletions(-)

diff --git a/utility/mcufriend_keil.h b/utility/mcufriend_keil.h
index 5ce3884..be6b55c 100644
--- a/utility/mcufriend_keil.h
+++ b/utility/mcufriend_keil.h
@@ -36,13 +36,50 @@
  #define RESET_IDLE    PIN_HIGH(RESET_PORT, RESET_PIN)
  #define RESET_OUTPUT  PIN_OUTPUT(RESET_PORT, RESET_PIN)
 
+#define WR_ACTIVE2  {WR_ACTIVE; WR_ACTIVE;}
+#define WR_ACTIVE4  {WR_ACTIVE2; WR_ACTIVE2;}
+#define WR_ACTIVE8  {WR_ACTIVE4; WR_ACTIVE4;}
+#define RD_ACTIVE2  {RD_ACTIVE; RD_ACTIVE;}
+#define RD_ACTIVE4  {RD_ACTIVE2; RD_ACTIVE2;}
+#define RD_ACTIVE8  {RD_ACTIVE4; RD_ACTIVE4;}
+#define RD_ACTIVE16 {RD_ACTIVE8; RD_ACTIVE8;}
+#define WR_IDLE2  {WR_IDLE; WR_IDLE;}
+#define WR_IDLE4  {WR_IDLE2; WR_IDLE2;}
+#define RD_IDLE2  {RD_IDLE; RD_IDLE;}
+#define RD_IDLE4  {RD_IDLE2; RD_IDLE2;}
+
 // General macros.   IOCLR registers are 1 cycle when optimised.
 #define WR_STROBE { WR_ACTIVE; WR_IDLE; }         //PWLW=TWRL=50ns
 #define RD_STROBE RD_IDLE, RD_ACTIVE, RD_ACTIVE, RD_ACTIVE   //PWLR=TRDL=150ns
 
 #if defined(TEENSY) || defined(__ARM_ARCH_7EM__) // -O2: F411@100MHz = 1.44s 
-#define WRITE_DELAY { WR_ACTIVE; WR_ACTIVE; WR_ACTIVE; WR_ACTIVE; }
-#define READ_DELAY  { RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; }
+//#define WRITE_DELAY { WR_ACTIVE; WR_ACTIVE; WR_ACTIVE; WR_ACTIVE; }
+//#define READ_DELAY  { RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; }
+#if 0
+#elif defined(STM32F401xx)
+#warning 84MHz
+#define WRITE_DELAY { WR_ACTIVE2; } //100MHz
+#define READ_DELAY  { RD_ACTIVE4; }
+#elif defined(STM32F411xx)
+#define WRITE_DELAY { WR_ACTIVE2; WR_ACTIVE; } //100MHz
+#define READ_DELAY  { RD_ACTIVE4; RD_ACTIVE2; }
+#elif defined(STM32F446xx)
+#warning 180MHz
+#define WRITE_DELAY { WR_ACTIVE8; } //180MHz
+#define IDLE_DELAY  { WR_IDLE2;WR_IDLE; }
+#define READ_DELAY  { RD_ACTIVE16;}
+#elif defined(STM32F767xx)
+#warning 216MHz
+#define WRITE_DELAY { WR_ACTIVE8; WR_ACTIVE8; } //216MHz
+#define IDLE_DELAY  { WR_IDLE4;WR_IDLE4; }
+#define READ_DELAY  { RD_ACTIVE16;RD_ACTIVE16;RD_ACTIVE16;}
+#elif defined(STM32H743xx) //STM32H743 GPIO needs testing
+#define WRITE_DELAY { WR_ACTIVE8;WR_ACTIVE2; } //F_CPU=400MHz
+#define IDLE_DELAY  { WR_IDLE2;WR_IDLE; }
+#define READ_DELAY  { RD_ACTIVE16;RD_ACTIVE16;RD_ACTIVE4;}
+#else 
+#error check specific STM32
+#endif
 #elif defined(__ARM_ARCH_7M__) // -O2: F103@72MHz = 2.68s
 #define WRITE_DELAY { }
 #define READ_DELAY  { RD_ACTIVE;  }
@@ -51,9 +88,13 @@
 #define READ_DELAY  { }
 #endif
 
-#define write8(x)     { write_8(x); WRITE_DELAY; WR_STROBE; WR_IDLE; }
+#ifndef IDLE_DELAY
+#define IDLE_DELAY    { WR_IDLE; }
+#endif
+
+#define write8(x)     { write_8(x); WRITE_DELAY; WR_STROBE; IDLE_DELAY; }
 #define write16(x)    { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
-#define READ_8(dst)   { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; RD_IDLE; } // read 250ns after RD_ACTIVE goes low
+#define READ_8(dst)   { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE2; RD_IDLE; } // read 250ns after RD_ACTIVE goes low
 #define READ_16(dst)  { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
 
 #define CTL_INIT()   { RD_OUTPUT; WR_OUTPUT; CD_OUTPUT; CS_OUTPUT; RESET_OUTPUT; }