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Merge remote-tracking branch 'refs/remotes/origin/test_Nucleo-F767'

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prenticedavid
2019-02-10 00:01:00 +00:00
parent c29987226c ed512ddc0e
commit 94a935c289
4 changed files with 245 additions and 24 deletions
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42
utility/mcufriend_mbed.h
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@@ -43,27 +43,53 @@ BusOut analog(A0, A1, A2, A3, A4, A5, NC, NC);
#define RESET_IDLE PIN_HIGH(RESET_PORT, RESET_PIN)
#define RESET_OUTPUT PIN_OUTPUT(RESET_PORT, RESET_PIN)
#define WR_ACTIVE2 {WR_ACTIVE; WR_ACTIVE;}
#define WR_ACTIVE4 {WR_ACTIVE2; WR_ACTIVE2;}
#define WR_ACTIVE8 {WR_ACTIVE4; WR_ACTIVE4;}
#define RD_ACTIVE2 {RD_ACTIVE; RD_ACTIVE;}
#define RD_ACTIVE4 {RD_ACTIVE2; RD_ACTIVE2;}
#define RD_ACTIVE8 {RD_ACTIVE4; RD_ACTIVE4;}
#define RD_ACTIVE16 {RD_ACTIVE8; RD_ACTIVE8;}
#define WR_IDLE2 {WR_IDLE; WR_IDLE;}
#define WR_IDLE4 {WR_IDLE2; WR_IDLE2;}
#define RD_IDLE2 {RD_IDLE; RD_IDLE;}
#define RD_IDLE4 {RD_IDLE2; RD_IDLE2;}
#if defined(__MK20DX128__) || defined(___MK20DX256__) // Teensy3.0 || 3.2 96MHz
#define WRITE_DELAY { WR_ACTIVE; WR_ACTIVE; }
#define READ_DELAY { RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; }
#define WRITE_DELAY { WR_ACTIVE2; }
#define READ_DELAY { RD_ACTIVE4; RD_ACTIVE; }
#elif defined(__MK64FX512__) || defined(TARGET_M4) // Teensy3.5 120MHz thanks to PeteJohno
#define WRITE_DELAY { WR_ACTIVE; WR_ACTIVE; WR_ACTIVE; WR_ACTIVE; }
#define READ_DELAY { RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; }
#define WRITE_DELAY { WR_ACTIVE4; }
#define READ_DELAY { RD_ACTIVE8; }
#elif defined(__MK66FX1M0__) || defined(TARGET_M4) // Teensy3.6 180MHz untested. delays can possibly be reduced.
#define WRITE_DELAY { WR_ACTIVE; WR_ACTIVE; WR_ACTIVE; WR_ACTIVE; WR_ACTIVE; WR_ACTIVE; WR_ACTIVE; WR_ACTIVE; }
#define READ_DELAY { RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; }
#define WRITE_DELAY { WR_ACTIVE8; }
#define READ_DELAY { RD_ACTIVE8; RD_ACTIVE8; }
#elif defined(TARGET_M7) // Nucleo-F767 216MHz untested. delays can possibly be reduced.
#define WRITE_DELAY { WR_ACTIVE8; WR_ACTIVE2; }
#define IDLE_DELAY { WR_IDLE2;WR_IDLE; }
#define READ_DELAY { RD_ACTIVE16; RD_ACTIVE16; RD_ACTIVE4; }
#define READ_IDLE { RD_IDLE2;RD_IDLE; }
#else
//#error unspecified delays
//#define WRITE_DELAY { WR_ACTIVE2; }
//#define READ_DELAY { RD_ACTIVE4; RD_ACTIVE; }
#define WRITE_DELAY
#define READ_DELAY
#endif
#if !defined(IDLE_DELAY)
#define IDLE_DELAY WR_IDLE
#endif
#if !defined(READ_IDLE)
#define READ_IDLE RD_IDLE
#endif
// General macros. IOCLR registers are 1 cycle when optimised.
#define WR_STROBE { WR_ACTIVE; WR_IDLE; } //PWLW=TWRL=50ns
#define RD_STROBE RD_IDLE, RD_ACTIVE, RD_ACTIVE, RD_ACTIVE //PWLR=TRDL=150ns
#define write8(d) { write_8(d); WRITE_DELAY; WR_STROBE; } // STROBEs are defined later
#define write8(d) { write_8(d); WRITE_DELAY; WR_STROBE; IDLE_DELAY; } // STROBEs are defined later
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; } // read 250ns after RD_ACTIVE goes low
#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); READ_IDLE; } // read 250ns after RD_ACTIVE goes low
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
#define CTL_INIT() { RD_OUTPUT; WR_OUTPUT; CD_OUTPUT; CS_OUTPUT; RESET_OUTPUT; }

118
utility/mcufriend_shield.h
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@@ -9,6 +9,8 @@
#define RD_ACTIVE16 {RD_ACTIVE8; RD_ACTIVE8;}
#define WR_IDLE2 {WR_IDLE; WR_IDLE;}
#define WR_IDLE4 {WR_IDLE2; WR_IDLE2;}
#define RD_IDLE2 {RD_IDLE; RD_IDLE;}
#define RD_IDLE4 {RD_IDLE2; RD_IDLE2;}
#if defined(USE_SPECIAL)
#include "mcufriend_special.h"
@@ -390,6 +392,10 @@ void write_8(uint8_t x)
|| defined(ARDUINO_NUCLEO_F446RE) || defined(ARDUINO_NUCLEO_L053R8) \
|| defined(ARDUINO_NUCLEO_L152RE) || defined(ARDUINO_NUCLEO_L476RG) \
)
#define IS_NUCLEO144 ( defined(ARDUINO_NUCLEO_F207ZG) \
|| defined(ARDUINO_NUCLEO_F429ZI) || defined(ARDUINO_NUCLEO_F767ZI) \
|| defined(ARDUINO_NUCLEO_L496ZG) || defined(ARDUINO_NUCLEO_L496ZG_P) \
)
// F1xx, F4xx, L4xx have different registers and styles. General Macros
#if defined(__STM32F1__) //weird Maple Core
#define REGS(x) regs->x
@@ -437,6 +443,14 @@ void write_8(uint8_t x)
#define GPIO_INIT() { RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN; }
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
#elif defined(STM32F207xx)
#warning DELAY macros untested yet
#define WRITE_DELAY { WR_ACTIVE8; } //120MHz
#define IDLE_DELAY { WR_IDLE2;WR_IDLE; }
#define READ_DELAY { RD_ACTIVE16;}
#define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN; }
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
#elif defined(STM32F303xE)
#define WRITE_DELAY { }
#define READ_DELAY { RD_ACTIVE8; } //thanks MasterT
@@ -445,24 +459,40 @@ void write_8(uint8_t x)
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) //thanks fpiSTM
#elif defined(STM32F401xE)
#define WRITE_DELAY { WR_ACTIVE2; }
#define WRITE_DELAY { WR_ACTIVE2; } //84MHz
#define READ_DELAY { RD_ACTIVE4; }
#define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN; }
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
#elif defined(STM32F411xE)
#define WRITE_DELAY { WR_ACTIVE2; WR_ACTIVE; }
#define WRITE_DELAY { WR_ACTIVE2; WR_ACTIVE; } //100MHz
#define READ_DELAY { RD_ACTIVE4; RD_ACTIVE2; }
#define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN; }
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
#elif defined(STM32F429xx)
#warning DELAY macros untested yet
#define WRITE_DELAY { WR_ACTIVE8; } //180MHz
#define IDLE_DELAY { WR_IDLE2;WR_IDLE; }
#define READ_DELAY { RD_ACTIVE16;}
#define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN; }
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
#elif defined(STM32F446xx)
#define WRITE_DELAY { WR_ACTIVE8; }
#define WRITE_DELAY { WR_ACTIVE8; } //180MHz
#define IDLE_DELAY { WR_IDLE2;WR_IDLE; }
#define READ_DELAY { RD_ACTIVE16;}
#define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN; }
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
#elif defined(STM32F767xx)
#warning DELAY macros untested yet
#define WRITE_DELAY { WR_ACTIVE8;WR_ACTIVE2; } //216MHz
#define IDLE_DELAY { WR_IDLE2;WR_IDLE; }
#define READ_DELAY { RD_ACTIVE16;RD_ACTIVE16;RD_ACTIVE4;}
#define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN; }
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
#elif defined(STM32L053xx)
#define WRITE_DELAY { }
#define READ_DELAY { RD_ACTIVE; }
@@ -476,11 +506,18 @@ void write_8(uint8_t x)
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
#elif defined(STM32L476xx)
#define WRITE_DELAY { WR_ACTIVE2; }
#define WRITE_DELAY { WR_ACTIVE2; } //80MHz
#define READ_DELAY { RD_ACTIVE4; RD_ACTIVE; }
#define GPIO_INIT() { RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOBEN | RCC_AHB2ENR_GPIOCEN; }
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
#elif defined(STM32L496xx)
#warning DELAY macros untested yet
#define WRITE_DELAY { WR_ACTIVE2; } //80MHz
#define READ_DELAY { RD_ACTIVE4; RD_ACTIVE; }
#define GPIO_INIT() { RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOCEN | RCC_AHB2ENR_GPIODEN | RCC_AHB2ENR_GPIOEEN | RCC_AHB2ENR_GPIOFEN; }
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
#else
#error unsupported STM32
#endif
@@ -507,24 +544,28 @@ void write_8(uint8_t x)
#define setWriteDir() {GP_OUT(GPIOA, CRL, 0xFFFFFFFF); }
#define setReadDir() {GP_INP(GPIOA, CRL, 0xFFFFFFFF); }
#elif IS_NUCLEO64 // Uno Shield on NUCLEO
#warning Uno Shield on NUCLEO
#define RD_PORT GPIOA
#elif IS_NUCLEO64 // Uno Shield on NUCLEO-64
#warning Uno Shield on NUCLEO-64
#define RD_PORT GPIOA //PA0
#define RD_PIN 0
#define WR_PORT GPIOA
#define WR_PORT GPIOA //PA1
#define WR_PIN 1
#define CD_PORT GPIOA
#define CD_PORT GPIOA //PA4
#define CD_PIN 4
#define CS_PORT GPIOB
#define CS_PORT GPIOB //PB0
#define CS_PIN 0
#define RESET_PORT GPIOC
#define RESET_PORT GPIOC //PC1
#define RESET_PIN 1
// configure macros for the data pins
#define AMASK ((1<<9)|(1<<10)|(1<<8)) //#0, #2, #7
#define BMASK ((1<<3)|(1<<5)|(1<<4)|(1<<10)) //#3, #4, #5, #6
#define CMASK ((1<<7)) //#1
#define write_8(d) { \
GPIOA->REGS(BSRR) = 0x0700 << 16; \
GPIOB->REGS(BSRR) = 0x0438 << 16; \
GPIOC->REGS(BSRR) = 0x0080 << 16; \
GPIOA->REGS(BSRR) = AMASK << 16; \
GPIOB->REGS(BSRR) = BMASK << 16; \
GPIOC->REGS(BSRR) = CMASK << 16; \
GPIOA->REGS(BSRR) = ( ((d) & (1<<0)) << 9) \
| (((d) & (1<<2)) << 8) \
| (((d) & (1<<7)) << 1); \
@@ -556,6 +597,53 @@ void write_8(uint8_t x)
#define setReadDir() { GPIOA->MODER &= ~0x3F0000; GPIOB->MODER &= ~0x300FC0; GPIOC->MODER &= ~0xC000; }
#endif
#elif IS_NUCLEO144 // Uno Shield on NUCLEO-144
#warning Uno Shield on NUCLEO-144
#define RD_PORT GPIOA //PA3
#define RD_PIN 3
#define WR_PORT GPIOC //PC0
#define WR_PIN 0
#define CD_PORT GPIOC //PC3
#define CD_PIN 3
#define CS_PORT GPIOF //PF3
#define CS_PIN 3
#define RESET_PORT GPIOF //PF5
#define RESET_PIN 5
// configure macros for the data pins
#define DMASK ((1<<15)) //#1
#define EMASK ((1<<13)|(1<<11)|(1<<9)) //#3, #5, #6
#define FMASK ((1<<12)|(1<<15)|(1<<14)|(1<<13)) //#0, #2, #4, #7
#define write_8(d) { \
GPIOD->REGS(BSRR) = DMASK << 16; \
GPIOE->REGS(BSRR) = EMASK << 16; \
GPIOF->REGS(BSRR) = FMASK << 16; \
GPIOD->REGS(BSRR) = ( ((d) & (1<<1)) << 14); \
GPIOE->REGS(BSRR) = ( ((d) & (1<<3)) << 10) \
| (((d) & (1<<5)) << 6) \
| (((d) & (1<<6)) << 3); \
GPIOF->REGS(BSRR) = ( ((d) & (1<<0)) << 12) \
| (((d) & (1<<2)) << 13) \
| (((d) & (1<<4)) << 10) \
| (((d) & (1<<7)) << 6); \
}
#define read_8() ( ( ( (GPIOF->REGS(IDR) & (1<<12)) >> 12) \
| ((GPIOD->REGS(IDR) & (1<<15)) >> 14) \
| ((GPIOF->REGS(IDR) & (1<<15)) >> 13) \
| ((GPIOE->REGS(IDR) & (1<<13)) >> 10) \
| ((GPIOF->REGS(IDR) & (1<<14)) >> 10) \
| ((GPIOE->REGS(IDR) & (1<<11)) >> 6) \
| ((GPIOE->REGS(IDR) & (1<<9)) >> 3) \
| ((GPIOF->REGS(IDR) & (1<<13)) >> 6)))
// PD15 PE13,PE11,PE9 PF15,PF14,PF13,PF12
#define setWriteDir() { setReadDir(); \
GPIOD->MODER |= 0x40000000; GPIOE->MODER |= 0x04440000; GPIOF->MODER |= 0x55000000; }
#define setReadDir() { GPIOD->MODER &= ~0xC0000000; GPIOE->MODER &= ~0x0CCC0000; GPIOF->MODER &= ~0xFF000000; }
#elif defined(ARDUINO_MAPLE_REV3) // Uno Shield on MAPLE_REV3 board
#warning Uno Shield on MAPLE_REV3 board
#define RD_PORT GPIOC
@@ -606,7 +694,7 @@ void write_8(uint8_t x)
#define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; IDLE_DELAY; }
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; RD_IDLE; }
#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE2; RD_IDLE; }
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
//################################### ESP32 ##############################

62
utility/pin_shield_1.h
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@@ -21,6 +21,10 @@
|| defined(TARGET_NUCLEO_L476RG) \
)
#define ISTARGET_NUCLEO144 (0 \
|| defined(TARGET_NUCLEO_F767ZI) \
)
//#warning Using pin_SHIELD_1.h
#if 0
@@ -192,6 +196,62 @@
#define PIN_OUTPUT(port, pin) {if (pin > 7) PIN_MODE4((port)->CRH, (pin&7), 0x3); else PIN_MODE4((port)->CRL, pin, 0x3); } //50MHz push-pull only 0-7
#define PIN_INPUT(port, pin) {if (pin > 7) PIN_MODE4((port)->CRH, (pin&7), 0x4); else PIN_MODE4((port)->CRL, pin, 0x4); } //input
#elif defined(NUCLEO144) || ISTARGET_NUCLEO144
#define PIN_MODE2(reg, pin, mode) reg=(reg&~(0x3<<((pin)<<1)))|(mode<<((pin)<<1))
#if __MBED__
#warning MBED knows everything
#elif defined(STM32F767xx)
#include <STM32F7XX.h>
#endif
#define D0_PORT GPIOG
#define D0_PIN 9
#define D1_PORT GPIOG
#define D1_PIN 14
#define D2_PORT GPIOF
#define D2_PIN 15
#define D3_PORT GPIOE
#define D3_PIN 13
#define D4_PORT GPIOF
#define D4_PIN 14
#define D5_PORT GPIOE
#define D5_PIN 11
#define D6_PORT GPIOE
#define D6_PIN 9
#define D7_PORT GPIOF
#define D7_PIN 13
#define D8_PORT GPIOF
#define D8_PIN 12
#define D9_PORT GPIOD
#define D9_PIN 15
#define D10_PORT GPIOD
#define D10_PIN 14
#define D11_PORT GPIOA
#define D11_PIN 7
#define D12_PORT GPIOA
#define D12_PIN 6
#define D13_PORT GPIOA
#define D13_PIN 5
#define A0_PORT GPIOA
#define A0_PIN 3
#define A1_PORT GPIOC
#define A1_PIN 0
#define A2_PORT GPIOC
#define A2_PIN 3
#define A3_PORT GPIOF
#define A3_PIN 3
#define A4_PORT GPIOF
#define A4_PIN 5
#define A5_PORT GPIOF
#define A5_PIN 10
// Shield Control macros
#define PIN_LOW(port, pin) (port)->BSRR = (1<<((pin)+16))
#define PIN_HIGH(port, pin) (port)->BSRR = (1<<(pin))
//#define PIN_LOW(port, pin) (port)->ODR &= ~(1<<(pin))
//#define PIN_HIGH(port, pin) (port)->ODR |= (1<<(pin))
#define PIN_READ(port, pin) (port)->IDR & (1<<(pin))
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
#define PIN_INPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x0) //.kbv check this
#elif defined(NUCLEO) || ISTARGET_NUCLEO64
#define PIN_MODE2(reg, pin, mode) reg=(reg&~(0x3<<((pin)<<1)))|(mode<<((pin)<<1))
@@ -474,7 +534,7 @@
#define PIN_INPUT(port, pin) (port)->PDDR &= ~(1u<<(pin))
#define PIN_READ(port, pin) (port)->PDIR & (1u<<(pin))
#elif defined(MKL05Z4)
#elif defined(MKL05Z4) || defined(TARGET_KL05Z)
#include <MKL05Z4.h>
#define D0_PORT PTB
#define D0_PIN 2

47
utility/pin_shield_8.h
View File

@@ -22,6 +22,10 @@
|| defined(TARGET_NUCLEO_L476RG) \
)
#define ISTARGET_NUCLEO144 (0 \
|| defined(TARGET_NUCLEO_F767ZI) \
)
//#warning Using pin_SHIELD_8.h
#if 0
@@ -94,6 +98,49 @@
#define setWriteDir() {GP_OUT(GPIOA, CRH, 0xFFF); GP_OUT(GPIOA, CRL, 0xFF); GP_OUT(GPIOB, CRL, 0xFFF00000); }
#define setReadDir() {GP_INP(GPIOA, CRH, 0xFFF); GP_INP(GPIOA, CRL, 0xFF); GP_INP(GPIOB, CRL, 0xFFF00000); }
#elif defined(NUCLEO144) || ISTARGET_NUCLEO144
#if __MBED__
#warning MBED knows everything
#elif defined(STM32F767xx)
#include <STM32F7XX.h>
#endif
#define REGS(x) x
// configure macros for the data pins
#define DMASK ((1<<15)) //#1
#define EMASK ((1<<13)|(1<<11)|(1<<9)) //#3, #5, #6
#define FMASK ((1<<12)|(1<<15)|(1<<14)|(1<<13)) //#0, #2, #4, #7
#define write_8(d) { \
GPIOD->REGS(BSRR) = DMASK << 16; \
GPIOE->REGS(BSRR) = EMASK << 16; \
GPIOF->REGS(BSRR) = FMASK << 16; \
GPIOD->REGS(BSRR) = ( ((d) & (1<<1)) << 14); \
GPIOE->REGS(BSRR) = ( ((d) & (1<<3)) << 10) \
| (((d) & (1<<5)) << 6) \
| (((d) & (1<<6)) << 3); \
GPIOF->REGS(BSRR) = ( ((d) & (1<<0)) << 12) \
| (((d) & (1<<2)) << 13) \
| (((d) & (1<<4)) << 10) \
| (((d) & (1<<7)) << 6); \
}
#define read_8() ( ( ( (GPIOF->REGS(IDR) & (1<<12)) >> 12) \
| ((GPIOD->REGS(IDR) & (1<<15)) >> 14) \
| ((GPIOF->REGS(IDR) & (1<<15)) >> 13) \
| ((GPIOE->REGS(IDR) & (1<<13)) >> 10) \
| ((GPIOF->REGS(IDR) & (1<<14)) >> 10) \
| ((GPIOE->REGS(IDR) & (1<<11)) >> 6) \
| ((GPIOE->REGS(IDR) & (1<<9)) >> 3) \
| ((GPIOF->REGS(IDR) & (1<<13)) >> 6)))
// PD15 PE13,PE11,PE9 PF15,PF14,PF13,PF12
#define setWriteDir() { setReadDir(); \
GPIOD->MODER |= 0x40000000; GPIOE->MODER |= 0x04440000; GPIOF->MODER |= 0x55000000; }
#define setReadDir() { GPIOD->MODER &= ~0xC0000000; GPIOE->MODER &= ~0x0CCC0000; GPIOF->MODER &= ~0xFF000000; }
#elif defined(NUCLEO) || ISTARGET_NUCLEO64
#if __MBED__
#warning MBED knows everything