From 721459a26474d07382c670a468dd411f8a6d229e Mon Sep 17 00:00:00 2001
From: prenticedavid <david.prentice@farming.co.uk>
Date: Thu, 13 Dec 2018 10:52:31 +0000
Subject: [PATCH] add pinouts for Nucleo-144

---
 utility/pin_shield_1.h | 60 ++++++++++++++++++++++++++++++++++++++++++
 utility/pin_shield_8.h | 47 +++++++++++++++++++++++++++++++++
 2 files changed, 107 insertions(+)

diff --git a/utility/pin_shield_1.h b/utility/pin_shield_1.h
index 8590206..824aaa6 100644
--- a/utility/pin_shield_1.h
+++ b/utility/pin_shield_1.h
@@ -21,6 +21,10 @@
         || defined(TARGET_NUCLEO_L476RG) \
         )
 
+#define ISTARGET_NUCLEO144 (0 \
+        || defined(TARGET_NUCLEO_F767ZI) \
+        )
+
 //#warning Using pin_SHIELD_1.h
 
 #if 0
@@ -192,6 +196,62 @@
 #define PIN_OUTPUT(port, pin) {if (pin > 7) PIN_MODE4((port)->CRH, (pin&7), 0x3); else  PIN_MODE4((port)->CRL, pin, 0x3); } //50MHz push-pull only 0-7
 #define PIN_INPUT(port, pin) {if (pin > 7) PIN_MODE4((port)->CRH, (pin&7), 0x4); else  PIN_MODE4((port)->CRL, pin, 0x4); }  //input
 
+
+#elif defined(NUCLEO144) || ISTARGET_NUCLEO144
+#define PIN_MODE2(reg, pin, mode) reg=(reg&~(0x3<<((pin)<<1)))|(mode<<((pin)<<1))
+#if __MBED__
+#warning MBED knows everything
+#elif defined(STM32F767xx)
+  #include <STM32F7XX.h>
+#endif
+  #define D0_PORT GPIOG
+  #define D0_PIN  9
+  #define D1_PORT GPIOG
+  #define D1_PIN  14
+  #define D2_PORT GPIOF
+  #define D2_PIN  15
+  #define D3_PORT GPIOE
+  #define D3_PIN  13
+  #define D4_PORT GPIOF
+  #define D4_PIN  14
+  #define D5_PORT GPIOE
+  #define D5_PIN  11
+  #define D6_PORT GPIOE
+  #define D6_PIN  9
+  #define D7_PORT GPIOF
+  #define D7_PIN  13
+  #define D8_PORT GPIOF
+  #define D8_PIN  12
+  #define D9_PORT GPIOD
+  #define D9_PIN  15
+  #define D10_PORT GPIOD
+  #define D10_PIN  14
+  #define D11_PORT GPIOA
+  #define D11_PIN  7
+  #define D12_PORT GPIOA
+  #define D12_PIN  6
+  #define D13_PORT GPIOA
+  #define D13_PIN  5
+  #define A0_PORT GPIOA
+  #define A0_PIN  3
+  #define A1_PORT GPIOC
+  #define A1_PIN  0
+  #define A2_PORT GPIOC
+  #define A2_PIN  3
+  #define A3_PORT GPIOF
+  #define A3_PIN  3
+  #define A4_PORT GPIOF
+  #define A4_PIN  5
+  #define A5_PORT GPIOF
+  #define A5_PIN  10
+// Shield Control macros
+#define PIN_LOW(port, pin)    (port)->BSRR = (1<<((pin)+16))
+#define PIN_HIGH(port, pin)   (port)->BSRR = (1<<(pin))
+//#define PIN_LOW(port, pin)    (port)->ODR &= ~(1<<(pin))
+//#define PIN_HIGH(port, pin)   (port)->ODR |=  (1<<(pin))
+#define PIN_READ(port, pin)   (port)->IDR & (1<<(pin))
+#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
+#define PIN_INPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x0)   //.kbv check this
 
 #elif defined(NUCLEO) || ISTARGET_NUCLEO64
 #define PIN_MODE2(reg, pin, mode) reg=(reg&~(0x3<<((pin)<<1)))|(mode<<((pin)<<1))
diff --git a/utility/pin_shield_8.h b/utility/pin_shield_8.h
index 2f662f7..ab4552b 100644
--- a/utility/pin_shield_8.h
+++ b/utility/pin_shield_8.h
@@ -22,6 +22,10 @@
         || defined(TARGET_NUCLEO_L476RG) \
         )
 
+#define ISTARGET_NUCLEO144 (0 \
+        || defined(TARGET_NUCLEO_F767ZI) \
+        )
+
 //#warning Using pin_SHIELD_8.h
 
 #if 0
@@ -94,6 +98,49 @@
 #define setWriteDir() {GP_OUT(GPIOA, CRH, 0xFFF); GP_OUT(GPIOA, CRL, 0xFF); GP_OUT(GPIOB, CRL, 0xFFF00000); }
 #define setReadDir()  {GP_INP(GPIOA, CRH, 0xFFF); GP_INP(GPIOA, CRL, 0xFF); GP_INP(GPIOB, CRL, 0xFFF00000); }
 
+#elif defined(NUCLEO144) || ISTARGET_NUCLEO144
+#if __MBED__
+#warning MBED knows everything
+#elif defined(STM32F767xx)
+  #include <STM32F7XX.h>
+#endif
+
+#define REGS(x) x
+// configure macros for the data pins
+#define DMASK ((1<<15))                         //#1
+#define EMASK ((1<<13)|(1<<11)|(1<<9))          //#3, #5, #6
+#define FMASK ((1<<12)|(1<<15)|(1<<14)|(1<<13)) //#0, #2, #4, #7
+
+#define write_8(d) { \
+        GPIOD->REGS(BSRR) = DMASK << 16; \
+        GPIOE->REGS(BSRR) = EMASK << 16; \
+        GPIOF->REGS(BSRR) = FMASK << 16; \
+        GPIOD->REGS(BSRR) = (  ((d) & (1<<1)) << 14); \
+        GPIOE->REGS(BSRR) = (  ((d) & (1<<3)) << 10) \
+                            | (((d) & (1<<5)) << 6) \
+                            | (((d) & (1<<6)) << 3); \
+        GPIOF->REGS(BSRR) = (  ((d) & (1<<0)) << 12) \
+                            | (((d) & (1<<2)) << 13) \
+                            | (((d) & (1<<4)) << 10) \
+                            | (((d) & (1<<7)) << 6); \
+    }
+
+#define read_8() (       (  (  (GPIOF->REGS(IDR) & (1<<12)) >> 12) \
+                            | ((GPIOD->REGS(IDR) & (1<<15)) >> 14) \
+                            | ((GPIOF->REGS(IDR) & (1<<15)) >> 13) \
+                            | ((GPIOE->REGS(IDR) & (1<<13)) >> 10) \
+                            | ((GPIOF->REGS(IDR) & (1<<14)) >> 10) \
+                            | ((GPIOE->REGS(IDR) & (1<<11)) >> 6) \
+                            | ((GPIOE->REGS(IDR) & (1<<9))  >> 3) \
+                            | ((GPIOF->REGS(IDR) & (1<<13)) >> 6)))
+
+
+//                                             PD15                PE13,PE11,PE9          PF15,PF14,PF13,PF12
+#define setWriteDir() { setReadDir(); \
+                        GPIOD->MODER |=  0x40000000; GPIOE->MODER |=  0x04440000; GPIOF->MODER |=  0x55000000; }
+#define setReadDir()  { GPIOD->MODER &= ~0xC0000000; GPIOE->MODER &= ~0x0CCC0000; GPIOF->MODER &= ~0xFF000000; }
+    
+
 #elif defined(NUCLEO) || ISTARGET_NUCLEO64
 #if __MBED__
 #warning MBED knows everything