mirror of
https://github.com/YuzuZensai/MCUFRIEND_kbv.git
synced 2026-01-06 04:32:38 +00:00
moved file layout for Arduino library style
This commit is contained in:
prenticedavid
243
utility/mcufriend_serial.h
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243
utility/mcufriend_serial.h
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#if ARDUINO >= 165
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#include <SPI.h>
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#endif
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#if 0
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#elif defined(__AVR_ATmega328P__)
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#define SPI_INIT() { DDRB |= (1<<5)|(1<<3)|(1<<2); SPCR = (1<<SPE)|(1<<MSTR); SPSR = (1<<SPI2X); SPSR; SPDR; }
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static inline uint8_t spi_xfer(uint8_t c)
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{
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SPDR = c;
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while ((SPSR & (1<<SPIF)) == 0) ;
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return SPDR;
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}
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extern uint8_t running;
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static inline void write8(uint8_t x) {
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if (running) {
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while ((SPSR & 0x80) == 0);
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SPDR;
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}
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SPDR = x;
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running = 1;
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}
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static inline uint8_t read8(void) {
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if (running) while ((SPSR & 0x80) == 0);
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running = 0;
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return SPDR;
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}
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static inline uint8_t xchg8(uint8_t x) { write8(x); return read8(); }
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static inline void flush(void) {
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if (running) {
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while ((SPSR & 0x80) == 0);
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}
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running = 0;
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SPDR;
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}
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#if defined(SUPPORT_8347D)
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#warning using HX8347D hardware
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#define CD_PORT PORTD
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#define CD_PIN PD7
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#define CS_PORT PORTB
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#define CS_PIN PB2
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#define RESET_PORT PORTB
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#define RESET_PIN PB1
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#define SD_PIN PD5
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#define XPT_PIN PD4
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#define RD_IDLE
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#define WR_IDLE
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#else
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#warning using regular SPI hardware
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#define CD_PORT PORTB
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#define CD_PIN 1
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#define CS_PORT PORTB
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#define CS_PIN 2
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#define RESET_PORT PORTB
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#define RESET_PIN 0
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#define RD_IDLE
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#define WR_IDLE
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#endif
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#define setWriteDir() { }
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#define setReadDir() { }
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//#define write8(x) spi_xfer(x)
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#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
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#define READ_8(dst) { dst = xchg8(0); }
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#define READ_16(dst) { dst = xchg8(0); dst = (dst << 8) | xchg8(0); }
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#define PIN_LOW(p, b) (p) &= ~(1<<(b))
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#define PIN_HIGH(p, b) (p) |= (1<<(b))
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#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
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#elif defined(__SAMD21G18A__)
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#define SPI_INIT() { SPI.begin(); SPI.setDataMode(SPI_MODE0); SPI.setClockDivider(6); }
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#define CD_PORT PORT->Group[0]
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#define CD_PIN 7
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#define CS_PORT PORT->Group[0]
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#define CS_PIN 18
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#define RESET_PORT PORT->Group[0]
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#define RESET_PIN 6
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#define RD_IDLE
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#define WR_IDLE
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uint8_t running;
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static inline void write8(uint8_t c)
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{
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running = 1;
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while( SERCOM1->SPI.INTFLAG.bit.DRE == 0) ;
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SERCOM1->SPI.DATA.bit.DATA = c; // Writing data into Data register
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}
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static inline void flush(void)
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{
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if (running) while( SERCOM1->SPI.INTFLAG.bit.TXC == 0) ;
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running = 0;
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}
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static inline uint8_t xchg8(uint8_t c)
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{
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// flush();
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while( SERCOM1->SPI.INTFLAG.bit.RXC != 0) SERCOM1->SPI.DATA.bit.DATA; //eat up
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while( SERCOM1->SPI.INTFLAG.bit.DRE == 0) ;
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SERCOM1->SPI.DATA.bit.DATA = c; // Writing data into Data register
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while( SERCOM1->SPI.INTFLAG.bit.RXC == 0) ;
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return SERCOM1->SPI.DATA.bit.DATA;
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}
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#define setWriteDir() { }
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#define setReadDir() { }
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//#define flush()
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//#define write8(x) xchg8(x)
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//#define xchg8(x) SPI.transfer(x)
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#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
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#define READ_8(dst) { dst = xchg8(0); }
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#define READ_16(dst) { dst = xchg8(0); dst = (dst << 8) | xchg8(0); }
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// Shield Control macros.
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#define PIN_LOW(port, pin) (port).OUTCLR.reg = (1<<(pin))
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#define PIN_HIGH(port, pin) (port).OUTSET.reg = (1<<(pin))
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#define PIN_OUTPUT(port, pin) (port).DIR.reg |= (1<<(pin))
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#elif defined(__AVR_ATxmega128A1__) //3.49s @ 32MHz -O2
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#define CD_PORT VPORT2
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#define CD_PIN 1
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#define CS_PORT VPORT3
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#define CS_PIN 4
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#define RESET_PORT VPORT2
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#define RESET_PIN 0
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#define SPCRVAL (USART_CLK2X_bm | USART_RXEN_bm | USART_TXEN_bm)
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#define SETDDR {VPORT3.DIR |= (1<<4)|(1<<5)|(1<<7); VPORT2.DIR |= 0x03; }
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#define SPI_INIT() { PORTCFG.VPCTRLB=PORTCFG_VP3MAP_PORTF_gc | PORTCFG_VP2MAP_PORTC_gc; CS_IDLE; RESET_IDLE; SETDDR; spi_init(); }
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void spi_init(void)
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{
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SPIF.CTRL=SPI_ENABLE_bm | SPI_MODE_3_gc | (1<<SPI_MASTER_bp) | (1<<SPI_CLK2X_bp);
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}
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#define write8(x) {\
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SPIF.DATA=x;\
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while ((SPIF.STATUS & SPI_IF_bm)==0);\
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SPIF.DATA;\
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}
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#define flush() {\
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}
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#define PIN_LOW(p, b) (p).OUT &= ~(1<<(b))
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#define PIN_HIGH(p, b) (p).OUT |= (1<<(b))
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#define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b))
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#elif defined(__AVR_ATxmega32A4U__) //3.49s @ 32MHz -O2.
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// 100ns/150ns for ILI9341 W/R cycle. 100ns/200ns for ILI920. 20ns/150ns HX8347
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// Xmega @ 60MHz i.e. 30MHz SCK works with 9341.
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#warning Using ATxmega32A4U USART_MSPI
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#define CD_PORT VPORT2
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#define CD_PIN 1
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#define CS_PORT VPORT3
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#define CS_PIN 0
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#define RESET_PORT VPORT2
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#define RESET_PIN 0
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#define SD_PORT PORTC
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#define SD_PIN 4
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#define SPCRVAL (USART_CLK2X_bm | USART_RXEN_bm | USART_TXEN_bm)
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#define SETDDR {PORTCFG.VPCTRLB=PORTCFG_VP13MAP_PORTD_gc | PORTCFG_VP02MAP_PORTC_gc; VPORT3.DIR |= (1<<0)|(1<<1)|(1<<3); VPORT2.DIR |= 0x03; PIN_HIGH(SD_PORT, SD_PIN); SD_PORT.DIR |= (1<<SD_PIN); }
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#define SPI_INIT() { CS_IDLE; RESET_IDLE; SETDDR; spi_init(); }
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static inline void spi_init(void)
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{
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USARTD0.CTRLB = SPCRVAL;
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USARTD0.CTRLC = USART_CMODE_MSPI_gc | 0x00 | 0x00; //mode #0
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// PORTD.PIN1CTRL |= PORT_INVEN_bm; //CPOL
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USARTD0.BAUDCTRLA = 0x00; //F_CPU/2
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USARTD0.BAUDCTRLB = ((0x00 << USART_BSCALE_gp) & USART_BSCALE_gm) | 0x00;
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USARTD0.DATA;
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}
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extern uint8_t running;
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#define write8(x) {\
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while ((USARTD0.STATUS & USART_DREIF_bm) == 0) ;\
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asm("cli");\
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USARTD0.DATA = x;\
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USARTD0.STATUS = USART_TXCIF_bm;\
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asm("sei");\
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running = 1;\
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}
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static inline uint8_t read8(void) {
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if (running) while ((USARTD0.STATUS & USART_RXCIF_bm) == 0) ;
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return USARTD0.DATA;
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}
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#define flush() {\
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if (running) while ((USARTD0.STATUS & USART_TXCIF_bm) == 0) ;\
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while ((USARTD0.STATUS & USART_RXCIF_bm) != 0) USARTD0.DATA;\
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running = 0;\
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}
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static inline uint8_t xchg8(uint8_t x) {
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USARTD0.DATA = x;
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while ((USARTD0.STATUS & USART_RXCIF_bm) == 0) ;
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return USARTD0.DATA;
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}
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/*
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#define write8(x) {\
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while ((USARTD0.STATUS & USART_DREIF_bm) == 0) ;\
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USARTD0.DATA = x;\
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while ((USARTD0.STATUS & USART_RXCIF_bm) == 0) ;\
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USARTD0.DATA;\
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}
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#define flush()
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*/
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#define RD_IDLE
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#define WR_IDLE
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//#define SPI_INIT() spi_init()
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#define setWriteDir() { }
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#define setReadDir() { }
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//#define write8(x) spi_xfer(x)
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#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
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#define READ_8(dst) { dst = xchg8(0); }
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#define READ_16(dst) { dst = xchg8(0); dst = (dst << 8) | xchg8(0); }
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#define PIN_LOW(p, b) (p).OUT &= ~(1<<(b))
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#define PIN_HIGH(p, b) (p).OUT |= (1<<(b))
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#define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b))
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#endif
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#define CD_COMMAND {flush(); PIN_LOW(CD_PORT, CD_PIN); }
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#define CD_DATA {flush(); PIN_HIGH(CD_PORT, CD_PIN); }
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#define CD_OUTPUT PIN_OUTPUT(CD_PORT, CD_PIN)
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#define CS_ACTIVE PIN_LOW(CS_PORT, CS_PIN)
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#define CS_IDLE {flush(); PIN_HIGH(CS_PORT, CS_PIN); }
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#define CS_OUTPUT PIN_OUTPUT(CS_PORT, CS_PIN)
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#define RESET_ACTIVE PIN_LOW(RESET_PORT, RESET_PIN)
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#define RESET_IDLE PIN_HIGH(RESET_PORT, RESET_PIN)
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#define RESET_OUTPUT PIN_OUTPUT(RESET_PORT, RESET_PIN)
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// General macros. IOCLR registers are 1 cycle when optimised.
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#define CTL_INIT() { CD_OUTPUT; CS_OUTPUT; RESET_OUTPUT; SPI_INIT(); }
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#define WriteCmd(x) { CD_COMMAND; write8(x); }
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#define WriteData(x) { CD_DATA; write16(x); }
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