mirror of
https://github.com/YuzuZensai/MCUFRIEND_kbv.git
synced 2026-01-31 14:57:48 +00:00
moved file layout for Arduino library style
This commit is contained in:
prenticedavid
61
utility/mcufriend_keil.h
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61
utility/mcufriend_keil.h
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@@ -0,0 +1,61 @@
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#ifndef MCUFRIEND_KEIL_H_
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#define MCUFRIEND_KEIL_H_
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#if defined(USE_SERIAL)
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#include "mcufriend_keil_spi.h"
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#else
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#include "pin_shield_1.h" //shield pin macros e.g. A2_PORT, PIN_OUTPUT()
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#include "pin_shield_8.h" //macros for write_8(), read_8(), setWriteDir(), ...
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// control pins as used in MCUFRIEND shields
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#define RD_PORT A0_PORT
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#define RD_PIN A0_PIN
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#define WR_PORT A1_PORT
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#define WR_PIN A1_PIN
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#define CD_PORT A2_PORT
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#define CD_PIN A2_PIN
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#define CS_PORT A3_PORT
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#define CS_PIN A3_PIN
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#define RESET_PORT A4_PORT
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#define RESET_PIN A4_PIN
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// general purpose pin macros
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#define RD_ACTIVE PIN_LOW(RD_PORT, RD_PIN)
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#define RD_IDLE PIN_HIGH(RD_PORT, RD_PIN)
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#define RD_OUTPUT PIN_OUTPUT(RD_PORT, RD_PIN)
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#define WR_ACTIVE PIN_LOW(WR_PORT, WR_PIN)
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#define WR_IDLE PIN_HIGH(WR_PORT, WR_PIN)
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#define WR_OUTPUT PIN_OUTPUT(WR_PORT, WR_PIN)
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#define CD_COMMAND PIN_LOW(CD_PORT, CD_PIN)
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#define CD_DATA PIN_HIGH(CD_PORT, CD_PIN)
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#define CD_OUTPUT PIN_OUTPUT(CD_PORT, CD_PIN)
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#define CS_ACTIVE PIN_LOW(CS_PORT, CS_PIN)
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#define CS_IDLE PIN_HIGH(CS_PORT, CS_PIN)
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#define CS_OUTPUT PIN_OUTPUT(CS_PORT, CS_PIN)
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#define RESET_ACTIVE PIN_LOW(RESET_PORT, RESET_PIN)
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#define RESET_IDLE PIN_HIGH(RESET_PORT, RESET_PIN)
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#define RESET_OUTPUT PIN_OUTPUT(RESET_PORT, RESET_PIN)
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// General macros. IOCLR registers are 1 cycle when optimised.
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#define WR_STROBE { WR_ACTIVE; WR_IDLE; } //PWLW=TWRL=50ns
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#define RD_STROBE RD_IDLE, RD_ACTIVE, RD_ACTIVE, RD_ACTIVE //PWLR=TRDL=150ns
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#if defined(TEENSY) || defined(__ARM_ARCH_7EM__) // || defined(STM32L476xx)
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#define write8(d) { write_8(d); WR_ACTIVE; WR_ACTIVE; WR_STROBE; } // STROBEs are defined later
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// read 250ns after RD_ACTIVE goes low
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#define read8() ( RD_STROBE, RD_ACTIVE, RD_ACTIVE, RD_ACTIVE, RD_ACTIVE, RD_ACTIVE, RD_ACTIVE, read_8() )
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#else
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#define write8(d) { write_8(d); WR_STROBE; } // STROBEs are defined later
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// read 250ns after RD_ACTIVE goes low
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#define read8() ( RD_STROBE, read_8() )
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#endif
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#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
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#define READ_8(dst) { dst = read8(); RD_IDLE; }
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#define READ_16(dst) { dst = read8(); dst = (dst<<8) | read8(); RD_IDLE; }
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#define CTL_INIT() { RD_OUTPUT; WR_OUTPUT; CD_OUTPUT; CS_OUTPUT; RESET_OUTPUT; }
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#define WriteCmd(x) { CD_COMMAND; write16(x); }
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#define WriteData(x) { CD_DATA; write16(x); }
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#endif //!USE_SERIAL
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#endif //MCUFRIEND_KEIL_H_
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243
utility/mcufriend_serial.h
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243
utility/mcufriend_serial.h
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@@ -0,0 +1,243 @@
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#if ARDUINO >= 165
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#include <SPI.h>
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#endif
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#if 0
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#elif defined(__AVR_ATmega328P__)
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#define SPI_INIT() { DDRB |= (1<<5)|(1<<3)|(1<<2); SPCR = (1<<SPE)|(1<<MSTR); SPSR = (1<<SPI2X); SPSR; SPDR; }
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static inline uint8_t spi_xfer(uint8_t c)
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{
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SPDR = c;
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while ((SPSR & (1<<SPIF)) == 0) ;
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return SPDR;
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}
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extern uint8_t running;
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static inline void write8(uint8_t x) {
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if (running) {
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while ((SPSR & 0x80) == 0);
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SPDR;
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}
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SPDR = x;
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running = 1;
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}
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static inline uint8_t read8(void) {
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if (running) while ((SPSR & 0x80) == 0);
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running = 0;
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return SPDR;
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}
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static inline uint8_t xchg8(uint8_t x) { write8(x); return read8(); }
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static inline void flush(void) {
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if (running) {
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while ((SPSR & 0x80) == 0);
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}
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running = 0;
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SPDR;
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}
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#if defined(SUPPORT_8347D)
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#warning using HX8347D hardware
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#define CD_PORT PORTD
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#define CD_PIN PD7
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#define CS_PORT PORTB
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#define CS_PIN PB2
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#define RESET_PORT PORTB
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#define RESET_PIN PB1
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#define SD_PIN PD5
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#define XPT_PIN PD4
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#define RD_IDLE
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#define WR_IDLE
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#else
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#warning using regular SPI hardware
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#define CD_PORT PORTB
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#define CD_PIN 1
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#define CS_PORT PORTB
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#define CS_PIN 2
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#define RESET_PORT PORTB
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#define RESET_PIN 0
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#define RD_IDLE
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#define WR_IDLE
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#endif
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#define setWriteDir() { }
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#define setReadDir() { }
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//#define write8(x) spi_xfer(x)
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#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
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#define READ_8(dst) { dst = xchg8(0); }
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#define READ_16(dst) { dst = xchg8(0); dst = (dst << 8) | xchg8(0); }
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#define PIN_LOW(p, b) (p) &= ~(1<<(b))
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#define PIN_HIGH(p, b) (p) |= (1<<(b))
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#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
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#elif defined(__SAMD21G18A__)
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#define SPI_INIT() { SPI.begin(); SPI.setDataMode(SPI_MODE0); SPI.setClockDivider(6); }
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#define CD_PORT PORT->Group[0]
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#define CD_PIN 7
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#define CS_PORT PORT->Group[0]
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#define CS_PIN 18
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#define RESET_PORT PORT->Group[0]
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#define RESET_PIN 6
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#define RD_IDLE
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#define WR_IDLE
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uint8_t running;
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static inline void write8(uint8_t c)
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{
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running = 1;
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while( SERCOM1->SPI.INTFLAG.bit.DRE == 0) ;
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SERCOM1->SPI.DATA.bit.DATA = c; // Writing data into Data register
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}
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static inline void flush(void)
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{
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if (running) while( SERCOM1->SPI.INTFLAG.bit.TXC == 0) ;
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running = 0;
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}
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static inline uint8_t xchg8(uint8_t c)
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{
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// flush();
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while( SERCOM1->SPI.INTFLAG.bit.RXC != 0) SERCOM1->SPI.DATA.bit.DATA; //eat up
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while( SERCOM1->SPI.INTFLAG.bit.DRE == 0) ;
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SERCOM1->SPI.DATA.bit.DATA = c; // Writing data into Data register
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while( SERCOM1->SPI.INTFLAG.bit.RXC == 0) ;
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return SERCOM1->SPI.DATA.bit.DATA;
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}
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#define setWriteDir() { }
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#define setReadDir() { }
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//#define flush()
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//#define write8(x) xchg8(x)
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//#define xchg8(x) SPI.transfer(x)
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#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
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#define READ_8(dst) { dst = xchg8(0); }
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#define READ_16(dst) { dst = xchg8(0); dst = (dst << 8) | xchg8(0); }
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// Shield Control macros.
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#define PIN_LOW(port, pin) (port).OUTCLR.reg = (1<<(pin))
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#define PIN_HIGH(port, pin) (port).OUTSET.reg = (1<<(pin))
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#define PIN_OUTPUT(port, pin) (port).DIR.reg |= (1<<(pin))
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#elif defined(__AVR_ATxmega128A1__) //3.49s @ 32MHz -O2
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#define CD_PORT VPORT2
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#define CD_PIN 1
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#define CS_PORT VPORT3
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#define CS_PIN 4
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#define RESET_PORT VPORT2
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#define RESET_PIN 0
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#define SPCRVAL (USART_CLK2X_bm | USART_RXEN_bm | USART_TXEN_bm)
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#define SETDDR {VPORT3.DIR |= (1<<4)|(1<<5)|(1<<7); VPORT2.DIR |= 0x03; }
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#define SPI_INIT() { PORTCFG.VPCTRLB=PORTCFG_VP3MAP_PORTF_gc | PORTCFG_VP2MAP_PORTC_gc; CS_IDLE; RESET_IDLE; SETDDR; spi_init(); }
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void spi_init(void)
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{
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SPIF.CTRL=SPI_ENABLE_bm | SPI_MODE_3_gc | (1<<SPI_MASTER_bp) | (1<<SPI_CLK2X_bp);
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}
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#define write8(x) {\
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SPIF.DATA=x;\
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while ((SPIF.STATUS & SPI_IF_bm)==0);\
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SPIF.DATA;\
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}
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#define flush() {\
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}
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#define PIN_LOW(p, b) (p).OUT &= ~(1<<(b))
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#define PIN_HIGH(p, b) (p).OUT |= (1<<(b))
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#define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b))
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#elif defined(__AVR_ATxmega32A4U__) //3.49s @ 32MHz -O2.
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// 100ns/150ns for ILI9341 W/R cycle. 100ns/200ns for ILI920. 20ns/150ns HX8347
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// Xmega @ 60MHz i.e. 30MHz SCK works with 9341.
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#warning Using ATxmega32A4U USART_MSPI
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#define CD_PORT VPORT2
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#define CD_PIN 1
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#define CS_PORT VPORT3
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#define CS_PIN 0
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#define RESET_PORT VPORT2
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#define RESET_PIN 0
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#define SD_PORT PORTC
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#define SD_PIN 4
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#define SPCRVAL (USART_CLK2X_bm | USART_RXEN_bm | USART_TXEN_bm)
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#define SETDDR {PORTCFG.VPCTRLB=PORTCFG_VP13MAP_PORTD_gc | PORTCFG_VP02MAP_PORTC_gc; VPORT3.DIR |= (1<<0)|(1<<1)|(1<<3); VPORT2.DIR |= 0x03; PIN_HIGH(SD_PORT, SD_PIN); SD_PORT.DIR |= (1<<SD_PIN); }
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#define SPI_INIT() { CS_IDLE; RESET_IDLE; SETDDR; spi_init(); }
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static inline void spi_init(void)
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{
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USARTD0.CTRLB = SPCRVAL;
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USARTD0.CTRLC = USART_CMODE_MSPI_gc | 0x00 | 0x00; //mode #0
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// PORTD.PIN1CTRL |= PORT_INVEN_bm; //CPOL
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USARTD0.BAUDCTRLA = 0x00; //F_CPU/2
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USARTD0.BAUDCTRLB = ((0x00 << USART_BSCALE_gp) & USART_BSCALE_gm) | 0x00;
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USARTD0.DATA;
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}
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extern uint8_t running;
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#define write8(x) {\
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while ((USARTD0.STATUS & USART_DREIF_bm) == 0) ;\
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asm("cli");\
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USARTD0.DATA = x;\
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USARTD0.STATUS = USART_TXCIF_bm;\
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asm("sei");\
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running = 1;\
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}
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static inline uint8_t read8(void) {
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if (running) while ((USARTD0.STATUS & USART_RXCIF_bm) == 0) ;
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return USARTD0.DATA;
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}
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#define flush() {\
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if (running) while ((USARTD0.STATUS & USART_TXCIF_bm) == 0) ;\
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while ((USARTD0.STATUS & USART_RXCIF_bm) != 0) USARTD0.DATA;\
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running = 0;\
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}
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static inline uint8_t xchg8(uint8_t x) {
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USARTD0.DATA = x;
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while ((USARTD0.STATUS & USART_RXCIF_bm) == 0) ;
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return USARTD0.DATA;
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}
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/*
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#define write8(x) {\
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while ((USARTD0.STATUS & USART_DREIF_bm) == 0) ;\
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USARTD0.DATA = x;\
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while ((USARTD0.STATUS & USART_RXCIF_bm) == 0) ;\
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USARTD0.DATA;\
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}
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#define flush()
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*/
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#define RD_IDLE
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#define WR_IDLE
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//#define SPI_INIT() spi_init()
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#define setWriteDir() { }
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#define setReadDir() { }
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//#define write8(x) spi_xfer(x)
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#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
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#define READ_8(dst) { dst = xchg8(0); }
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#define READ_16(dst) { dst = xchg8(0); dst = (dst << 8) | xchg8(0); }
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#define PIN_LOW(p, b) (p).OUT &= ~(1<<(b))
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#define PIN_HIGH(p, b) (p).OUT |= (1<<(b))
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#define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b))
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#endif
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#define CD_COMMAND {flush(); PIN_LOW(CD_PORT, CD_PIN); }
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#define CD_DATA {flush(); PIN_HIGH(CD_PORT, CD_PIN); }
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#define CD_OUTPUT PIN_OUTPUT(CD_PORT, CD_PIN)
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#define CS_ACTIVE PIN_LOW(CS_PORT, CS_PIN)
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#define CS_IDLE {flush(); PIN_HIGH(CS_PORT, CS_PIN); }
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#define CS_OUTPUT PIN_OUTPUT(CS_PORT, CS_PIN)
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#define RESET_ACTIVE PIN_LOW(RESET_PORT, RESET_PIN)
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#define RESET_IDLE PIN_HIGH(RESET_PORT, RESET_PIN)
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#define RESET_OUTPUT PIN_OUTPUT(RESET_PORT, RESET_PIN)
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// General macros. IOCLR registers are 1 cycle when optimised.
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#define CTL_INIT() { CD_OUTPUT; CS_OUTPUT; RESET_OUTPUT; SPI_INIT(); }
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#define WriteCmd(x) { CD_COMMAND; write8(x); }
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#define WriteData(x) { CD_DATA; write16(x); }
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457
utility/mcufriend_shield.h
Normal file
457
utility/mcufriend_shield.h
Normal file
@@ -0,0 +1,457 @@
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//#define USE_SPECIAL //check for custom drivers
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#if defined(USE_SPECIAL)
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#include "mcufriend_special.h"
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#if !defined(USE_SPECIAL_FAIL)
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#warning WE ARE USING A SPECIAL CUSTOM DRIVER
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#endif
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#endif
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#if !defined(USE_SPECIAL) || defined (USE_SPECIAL_FAIL)
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#if 0
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#elif defined(__AVR_ATmega328P__) //regular UNO shield on UNO
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#define RD_PORT PORTC
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#define RD_PIN 0
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#define WR_PORT PORTC
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#define WR_PIN 1
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#define CD_PORT PORTC
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#define CD_PIN 2
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#define CS_PORT PORTC
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#define CS_PIN 3
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#define RESET_PORT PORTC
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#define RESET_PIN 4
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#define DMASK 0x03
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#define NMASK ~DMASK
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#define write_8(x) { PORTB = (PORTB & NMASK) | ((x) & DMASK); PORTD = (PORTD & DMASK) | ((x) & NMASK); }
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#define read_8() ( (PINB & DMASK) | (PIND & NMASK) )
|
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#define setWriteDir() { DDRB = (DDRB & NMASK) | DMASK; DDRD = (DDRD & DMASK) | NMASK; }
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#define setReadDir() { DDRB = (DDRB & NMASK) & NMASK; DDRD = (DDRD & DMASK) & DMASK; }
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#define write8(x) { write_8(x); WR_STROBE; }
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#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
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#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
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#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
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#define PIN_LOW(p, b) (p) &= ~(1<<(b))
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#define PIN_HIGH(p, b) (p) |= (1<<(b))
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#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
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#elif defined(__AVR_ATmega2560__) || defined(__AVR_ATmega1280__) //regular UNO shield on MEGA2560
|
||||
#define RD_PORT PORTF
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#define RD_PIN 0
|
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#define WR_PORT PORTF
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#define WR_PIN 1
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#define CD_PORT PORTF
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#define CD_PIN 2
|
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#define CS_PORT PORTF
|
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#define CS_PIN 3
|
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#define RESET_PORT PORTF
|
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#define RESET_PIN 4
|
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|
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#define EMASK 0x38
|
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#define GMASK 0x20
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#define HMASK 0x78
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#define write_8(x) { PORTH &= ~HMASK; PORTG &= ~GMASK; PORTE &= ~EMASK; \
|
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PORTH |= (((x) & (3<<0)) << 5); \
|
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PORTE |= (((x) & (3<<2)) << 2); \
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PORTG |= (((x) & (1<<4)) << 1); \
|
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PORTE |= (((x) & (1<<5)) >> 2); \
|
||||
PORTH |= (((x) & (3<<6)) >> 3); \
|
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}
|
||||
|
||||
#define read_8() ( ((PINH & (3<<5)) >> 5)\
|
||||
| ((PINE & (3<<4)) >> 2)\
|
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| ((PING & (1<<5)) >> 1)\
|
||||
| ((PINE & (1<<3)) << 2)\
|
||||
| ((PINH & (3<<3)) << 3)\
|
||||
)
|
||||
#define setWriteDir() { DDRH |= HMASK; DDRG |= GMASK; DDRE |= EMASK; }
|
||||
#define setReadDir() { DDRH &= ~HMASK; DDRG &= ~GMASK; DDRE &= ~EMASK; }
|
||||
#define write8(x) { write_8(x); WR_STROBE; }
|
||||
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
|
||||
#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
|
||||
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
|
||||
|
||||
#define PIN_LOW(p, b) (p) &= ~(1<<(b))
|
||||
#define PIN_HIGH(p, b) (p) |= (1<<(b))
|
||||
#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
|
||||
|
||||
#elif defined(__SAMD21G18A__) //regular UNO shield on ZERO or M0_PRO
|
||||
#include "sam.h"
|
||||
// configure macros for the control pins
|
||||
#define RD_PORT PORT->Group[0]
|
||||
#define RD_PIN 2
|
||||
#define WR_PORT PORT->Group[1]
|
||||
#define WR_PIN 8
|
||||
#define CD_PORT PORT->Group[1]
|
||||
#define CD_PIN 9
|
||||
#define CS_PORT PORT->Group[0]
|
||||
#define CS_PIN 4
|
||||
#define RESET_PORT PORT->Group[0]
|
||||
#define RESET_PIN 5
|
||||
// configure macros for data bus
|
||||
#define DMASK 0x0030C3C0
|
||||
// #define write_8(x) PORT->Group[0].OUT.reg = (PORT->Group[0].OUT.reg & ~DMASK)|(((x) & 0x0F) << 6)|(((x) & 0x30) << 10)|(((x) & 0xC0)<<14)
|
||||
#if defined(ARDUINO_SAMD_ZERO) || defined(ARDUINO_SAMD_ZERO) // American ZERO
|
||||
#define write_8(x) {\
|
||||
PORT->Group[0].OUTCLR.reg = DMASK;\
|
||||
PORT->Group[0].OUTSET.reg = (((x) & 0x0B) << 6)\
|
||||
|(((x) & (1<<2)) << 12)\
|
||||
|(((x) & (1<<4)) << 4)\
|
||||
|(((x) & (1<<5)) << 10)\
|
||||
|(((x) & 0xC0) << 14);\
|
||||
}
|
||||
#define read_8() (((PORT->Group[0].IN.reg >> 6) & 0x0B)\
|
||||
|((PORT->Group[0].IN.reg >> 12) & (1<<2))\
|
||||
|((PORT->Group[0].IN.reg >> 4) & (1<<4))\
|
||||
|((PORT->Group[0].IN.reg >> 10) & (1<<5))\
|
||||
|((PORT->Group[0].IN.reg >> 14) & 0xC0))
|
||||
#else //default to an M0_PRO on v1.6.5 or 1.7.6
|
||||
#define write_8(x) {\
|
||||
PORT->Group[0].OUTCLR.reg = DMASK;\
|
||||
PORT->Group[0].OUTSET.reg = (((x) & 0x0F) << 6)\
|
||||
|(((x) & 0x30) << 10)\
|
||||
|(((x) & 0xC0) << 14);\
|
||||
}
|
||||
#define read_8() (((PORT->Group[0].IN.reg >> 6) & 0x0F)|((PORT->Group[0].IN.reg >> 10) & 0x30)|((PORT->Group[0].IN.reg >> 14) & 0xC0))
|
||||
#endif
|
||||
#define setWriteDir() { PORT->Group[0].DIRSET.reg = DMASK; \
|
||||
PORT->Group[0].WRCONFIG.reg = (DMASK & 0xFFFF) | (0<<22) | (1<<28) | (1<<30); \
|
||||
PORT->Group[0].WRCONFIG.reg = (DMASK>>16) | (0<<22) | (1<<28) | (1<<30) | (1<<31); \
|
||||
}
|
||||
#define setReadDir() { PORT->Group[0].DIRCLR.reg = DMASK; \
|
||||
PORT->Group[0].WRCONFIG.reg = (DMASK & 0xFFFF) | (1<<17) | (1<<28) | (1<<30); \
|
||||
PORT->Group[0].WRCONFIG.reg = (DMASK>>16) | (1<<17) | (1<<28) | (1<<30) | (1<<31); \
|
||||
}
|
||||
#define write8(x) { write_8(x); WR_ACTIVE; WR_STROBE; }
|
||||
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
|
||||
#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
|
||||
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
|
||||
// Shield Control macros.
|
||||
#define PIN_LOW(port, pin) (port).OUTCLR.reg = (1<<(pin))
|
||||
#define PIN_HIGH(port, pin) (port).OUTSET.reg = (1<<(pin))
|
||||
#define PIN_OUTPUT(port, pin) (port).DIR.reg |= (1<<(pin))
|
||||
|
||||
#elif defined(__SAM3X8E__) //regular UNO shield on DUE
|
||||
// configure macros for the control pins
|
||||
#define RD_PORT PIOA
|
||||
#define RD_PIN 16
|
||||
#define WR_PORT PIOA
|
||||
#define WR_PIN 24
|
||||
#define CD_PORT PIOA
|
||||
#define CD_PIN 23
|
||||
#define CS_PORT PIOA
|
||||
#define CS_PIN 22
|
||||
#define RESET_PORT PIOA
|
||||
#define RESET_PIN 6
|
||||
// configure macros for data bus
|
||||
#define BMASK (1<<25)
|
||||
#define CMASK (0xBF << 21)
|
||||
#define write_8(x) { PIOB->PIO_CODR = BMASK; PIOC->PIO_CODR = CMASK; \
|
||||
PIOC->PIO_SODR = (((x) & (1<<0)) << 22); \
|
||||
PIOC->PIO_SODR = (((x) & (1<<1)) << 20); \
|
||||
PIOB->PIO_SODR = (((x) & (1<<2)) << 23); \
|
||||
PIOC->PIO_SODR = (((x) & (1<<3)) << 25); \
|
||||
PIOC->PIO_SODR = (((x) & (1<<4)) << 22); \
|
||||
PIOC->PIO_SODR = (((x) & (1<<5)) << 20); \
|
||||
PIOC->PIO_SODR = (((x) & (1<<6)) << 18); \
|
||||
PIOC->PIO_SODR = (((x) & (1<<7)) << 16); \
|
||||
}
|
||||
|
||||
#define read_8() ( ((PIOC->PIO_PDSR & (1<<22)) >> 22)\
|
||||
| ((PIOC->PIO_PDSR & (1<<21)) >> 20)\
|
||||
| ((PIOB->PIO_PDSR & (1<<25)) >> 23)\
|
||||
| ((PIOC->PIO_PDSR & (1<<28)) >> 25)\
|
||||
| ((PIOC->PIO_PDSR & (1<<26)) >> 22)\
|
||||
| ((PIOC->PIO_PDSR & (1<<25)) >> 20)\
|
||||
| ((PIOC->PIO_PDSR & (1<<24)) >> 18)\
|
||||
| ((PIOC->PIO_PDSR & (1<<23)) >> 16)\
|
||||
)
|
||||
#define setWriteDir() { PIOB->PIO_OER = BMASK; PIOC->PIO_OER = CMASK; }
|
||||
#define setReadDir() { \
|
||||
PMC->PMC_PCER0 = (1 << ID_PIOB)|(1 << ID_PIOC);\
|
||||
PIOB->PIO_ODR = BMASK; PIOC->PIO_ODR = CMASK;\
|
||||
}
|
||||
#define write8(x) { write_8(x); WR_ACTIVE; WR_STROBE; }
|
||||
//#define write8(x) { write_8(x); WR_ACTIVE; WR_STROBE; WR_IDLE; }
|
||||
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
|
||||
#define READ_8(dst) { RD_STROBE; RD_ACTIVE; dst = read_8(); RD_IDLE; RD_IDLE; }
|
||||
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
|
||||
// Shield Control macros.
|
||||
#define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin))
|
||||
#define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin))
|
||||
#define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin))
|
||||
|
||||
#elif defined(__AVR_ATmega32U4__) //regular UNO shield on Leonardo
|
||||
#define RD_PORT PORTF
|
||||
#define RD_PIN 7
|
||||
#define WR_PORT PORTF
|
||||
#define WR_PIN 6
|
||||
#define CD_PORT PORTF
|
||||
#define CD_PIN 5
|
||||
#define CS_PORT PORTF
|
||||
#define CS_PIN 4
|
||||
#define RESET_PORT PORTF
|
||||
#define RESET_PIN 1
|
||||
|
||||
#define BMASK (3<<4)
|
||||
#define CMASK (1<<6)
|
||||
#define DMASK ((1<<7)|(1<<4)|(3<<0))
|
||||
#define EMASK (1<<6)
|
||||
static inline //hope we use r24
|
||||
void write_8(uint8_t x)
|
||||
{
|
||||
PORTB &= ~BMASK;
|
||||
PORTC &= ~CMASK;
|
||||
PORTD &= ~DMASK;
|
||||
PORTE &= ~EMASK;
|
||||
PORTB |= (((x) & (3 << 0)) << 4);
|
||||
PORTD |= (((x) & (1 << 2)) >> 1);
|
||||
PORTD |= (((x) & (1 << 3)) >> 3);
|
||||
PORTD |= (((x) & (1 << 4)) << 0);
|
||||
PORTC |= (((x) & (1 << 5)) << 1);
|
||||
PORTD |= (((x) & (1 << 6)) << 1);
|
||||
PORTE |= (((x) & (1 << 7)) >> 1);
|
||||
}
|
||||
|
||||
#define read_8() ( ((PINB & (3<<4)) >> 4)\
|
||||
| ((PIND & (1<<1)) << 1)\
|
||||
| ((PIND & (1<<0)) << 3)\
|
||||
| ((PIND & (1<<4)) >> 0)\
|
||||
| ((PINC & (1<<6)) >> 1)\
|
||||
| ((PIND & (1<<7)) >> 1)\
|
||||
| ((PINE & (1<<6)) << 1)\
|
||||
)
|
||||
#define setWriteDir() { DDRB |= BMASK; DDRC |= CMASK; DDRD |= DMASK; DDRE |= EMASK; }
|
||||
#define setReadDir() { DDRB &= ~BMASK; DDRC &= ~CMASK; DDRD &= ~DMASK; DDRE &= ~EMASK; }
|
||||
#define write8(x) { write_8(x); WR_STROBE; }
|
||||
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
|
||||
#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
|
||||
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
|
||||
|
||||
#define PIN_LOW(p, b) (p) &= ~(1<<(b))
|
||||
#define PIN_HIGH(p, b) (p) |= (1<<(b))
|
||||
#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
|
||||
|
||||
#elif defined(__MK20DX128__) || defined(__MK20DX256__) // regular UNO shield on a Teensy 3.x
|
||||
#warning regular UNO shield on a Teensy 3.x
|
||||
#define RD_PORT GPIOD
|
||||
#define RD_PIN 1
|
||||
#define WR_PORT GPIOC
|
||||
#define WR_PIN 0
|
||||
#define CD_PORT GPIOB
|
||||
#define CD_PIN 0
|
||||
#define CS_PORT GPIOB
|
||||
#define CS_PIN 1
|
||||
#define RESET_PORT GPIOB
|
||||
#define RESET_PIN 3
|
||||
|
||||
// configure macros for the data pins
|
||||
#define AMASK ((1<<12)|(1<<13))
|
||||
#define CMASK ((1<<3))
|
||||
#define DMASK ((1<<0)|(1<<2)|(1<<3)|(1<<4)|(1<<7))
|
||||
|
||||
#define write_8(d) { \
|
||||
GPIOA_PCOR = AMASK; GPIOC_PCOR = CMASK; GPIOD_PCOR = DMASK; \
|
||||
GPIOA_PSOR = (((d) & (1<<3)) << 9) \
|
||||
| (((d) & (1<<4)) << 9); \
|
||||
GPIOC_PSOR = (((d) & (1<<1)) << 2); \
|
||||
GPIOD_PSOR = (((d) & (1<<0)) << 3) \
|
||||
| (((d) & (1<<2)) >> 2) \
|
||||
| (((d) & (1<<5)) << 2) \
|
||||
| (((d) & (1<<6)) >> 2) \
|
||||
| (((d) & (1<<7)) >> 5); \
|
||||
}
|
||||
#define read_8() ( (((GPIOD_PDIR & (1<<3)) >> 3) \
|
||||
| ((GPIOC_PDIR & (1<<3)) >> 2) \
|
||||
| ((GPIOD_PDIR & (1<<0)) << 2) \
|
||||
| ((GPIOA_PDIR & (1<<12)) >> 9) \
|
||||
| ((GPIOA_PDIR & (1<<13)) >> 9) \
|
||||
| ((GPIOD_PDIR & (1<<7)) >> 2) \
|
||||
| ((GPIOD_PDIR & (1<<4)) << 2) \
|
||||
| ((GPIOD_PDIR & (1<<2)) << 5)))
|
||||
#define setWriteDir() {GPIOA_PDDR |= AMASK;GPIOC_PDDR |= CMASK;GPIOD_PDDR |= DMASK; }
|
||||
#define setReadDir() {GPIOA_PDDR &= ~AMASK;GPIOC_PDDR &= ~CMASK;GPIOD_PDDR &= ~DMASK; }
|
||||
|
||||
#define write8(x) { write_8(x); WR_ACTIVE; WR_ACTIVE; WR_STROBE; }
|
||||
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
|
||||
#define READ_8(dst) { RD_STROBE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; dst = read_8(); RD_IDLE; }
|
||||
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
|
||||
|
||||
#define PASTE(x, y) x ## y
|
||||
|
||||
#define PIN_LOW(port, pin) PASTE(port, _PCOR) = (1<<(pin))
|
||||
#define PIN_HIGH(port, pin) PASTE(port, _PSOR) = (1<<(pin))
|
||||
#define PIN_OUTPUT(port, pin) PASTE(port, _PDDR) |= (1<<(pin))
|
||||
|
||||
#elif defined(__STM32F1__) && defined(ARDUINO_STM_NUCLEO_F103RB) // Uno Shield on NUCLEO-F103
|
||||
#warning Uno Shield on NUCLEO-F103 REGS
|
||||
// be wise to clear all four mode bits properly.
|
||||
#define GROUP_MODE(port, reg, mask, val) {port->regs->reg = (port->regs->reg & ~(mask)) | ((mask)&(val)); }
|
||||
#define GP_OUT(port, reg, mask) GROUP_MODE(port, reg, mask, 0x33333333)
|
||||
#define GP_INP(port, reg, mask) GROUP_MODE(port, reg, mask, 0x44444444)
|
||||
|
||||
#define RD_PORT GPIOA
|
||||
#define RD_PIN 0
|
||||
#define WR_PORT GPIOA
|
||||
#define WR_PIN 1
|
||||
#define CD_PORT GPIOA
|
||||
#define CD_PIN 4
|
||||
#define CS_PORT GPIOB
|
||||
#define CS_PIN 0
|
||||
#define RESET_PORT GPIOC
|
||||
#define RESET_PIN 1
|
||||
|
||||
// configure macros for the data pins
|
||||
#define write_8(d) { \
|
||||
GPIOA->regs->BSRR = 0x0700 << 16; \
|
||||
GPIOB->regs->BSRR = 0x0438 << 16; \
|
||||
GPIOC->regs->BSRR = 0x0080 << 16; \
|
||||
GPIOA->regs->BSRR = (((d) & (1<<0)) << 9) \
|
||||
| (((d) & (1<<2)) << 8) \
|
||||
| (((d) & (1<<7)) << 1); \
|
||||
GPIOB->regs->BSRR = (((d) & (1<<3)) << 0) \
|
||||
| (((d) & (1<<4)) << 1) \
|
||||
| (((d) & (1<<5)) >> 1) \
|
||||
| (((d) & (1<<6)) << 4); \
|
||||
GPIOC->regs->BSRR = (((d) & (1<<1)) << 6); \
|
||||
}
|
||||
|
||||
#define read_8() ( (((GPIOA->regs->IDR & (1<<9)) >> 9) \
|
||||
| ((GPIOC->regs->IDR & (1<<7)) >> 6) \
|
||||
| ((GPIOA->regs->IDR & (1<<10)) >> 8) \
|
||||
| ((GPIOB->regs->IDR & (1<<3)) >> 0) \
|
||||
| ((GPIOB->regs->IDR & (1<<5)) >> 1) \
|
||||
| ((GPIOB->regs->IDR & (1<<4)) << 1) \
|
||||
| ((GPIOB->regs->IDR & (1<<10)) >> 4) \
|
||||
| ((GPIOA->regs->IDR & (1<<8)) >> 1)))
|
||||
|
||||
// PA10,PA9,PA8 PB10 PB5,PB4,PB3 PC7
|
||||
#define setWriteDir() {GP_OUT(GPIOA, CRH, 0xFFF); GP_OUT(GPIOB, CRH, 0xF00); GP_OUT(GPIOB, CRL, 0xFFF000); GP_OUT(GPIOC, CRL, 0xF0000000); }
|
||||
#define setReadDir() {GP_INP(GPIOA, CRH, 0xFFF); GP_INP(GPIOB, CRH, 0xF00); GP_INP(GPIOB, CRL, 0xFFF000); GP_INP(GPIOC, CRL, 0xF0000000); }
|
||||
|
||||
#define write8(x) { write_8(x); WR_ACTIVE; WR_STROBE; }
|
||||
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
|
||||
#define READ_8(dst) { RD_STROBE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; dst = read_8(); RD_IDLE; }
|
||||
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
|
||||
|
||||
#define PIN_HIGH(port, pin) (port)->regs->BSRR = (1<<(pin))
|
||||
//#define PIN_LOW(port, pin) (port)->regs->BSRR = (1<<((pin)+16))
|
||||
#define PIN_LOW(port, pin) (port)->regs->ODR &= ~(1<<(pin))
|
||||
#if 0
|
||||
#define PIN_OUTPUT(port, pin) { \
|
||||
if (pin < 8) { GP_OUT(port, CRL, 0xF<<((pin)<<2)); } \
|
||||
else { GP_OUT(port, CRH, 0xF<<((pin-8)<<2)); } \
|
||||
}
|
||||
#define PIN_INPUT(port, pin) { \
|
||||
if (pin < 8) { GP_INP(port, CRL, 0xF<<((pin)<<2)); } \
|
||||
else { GP_INP(port, CRH, 0xF<<((pin-8)<<2)); } \
|
||||
}
|
||||
#elif 1
|
||||
#define PIN_OUTPUT(port, pin) gpio_set_mode(port, pin, GPIO_OUTPUT_PP) //50MHz push-pull only 0-7
|
||||
#define PIN_INPUT(port, pin) gpio_set_mode(port, pin, GPIO_INPUT_FLOATING) //digital input
|
||||
#else
|
||||
#define PIN_OUTPUT(port, pin) GP_OUT(port, CRL, 0xF<<((pin)<<2)) //50MHz push-pull only 0-7
|
||||
#define PIN_INPUT(port, pin) GP_INP(port, CRL, 0xF<<((pin)<<2)) //digital input
|
||||
#endif
|
||||
|
||||
//#elif defined(__STM32F1__) && defined(ARDUINO_GENERIC_STM32F103R)
|
||||
#elif defined(__STM32F1__) && defined(ARDUINO_MAPLE_REV3) // Uno Shield on MAPLE_REV3 board
|
||||
#warning Uno Shield on MAPLE_REV3 board
|
||||
// be wise to clear all four mode bits properly.
|
||||
#define GROUP_MODE(port, reg, mask, val) {port->regs->reg = (port->regs->reg & ~(mask)) | ((mask)&(val)); }
|
||||
#define GP_OUT(port, reg, mask) GROUP_MODE(port, reg, mask, 0x33333333)
|
||||
#define GP_INP(port, reg, mask) GROUP_MODE(port, reg, mask, 0x44444444)
|
||||
|
||||
#define RD_PORT GPIOC
|
||||
#define RD_PIN 0
|
||||
#define WR_PORT GPIOC
|
||||
#define WR_PIN 1
|
||||
#define CD_PORT GPIOC
|
||||
#define CD_PIN 2
|
||||
#define CS_PORT GPIOC
|
||||
#define CS_PIN 3
|
||||
#define RESET_PORT GPIOC
|
||||
#define RESET_PIN 4
|
||||
|
||||
// configure macros for the data pins
|
||||
#define write_8(d) { \
|
||||
GPIOA->regs->BSRR = 0x0703 << 16; \
|
||||
GPIOB->regs->BSRR = 0x00E0 << 16; \
|
||||
GPIOA->regs->BSRR = (((d) & (1<<0)) << 10) \
|
||||
| (((d) & (1<<2)) >> 2) \
|
||||
| (((d) & (1<<3)) >> 2) \
|
||||
| (((d) & (1<<6)) << 2) \
|
||||
| (((d) & (1<<7)) << 2); \
|
||||
GPIOB->regs->BSRR = (((d) & (1<<1)) << 6) \
|
||||
| (((d) & (1<<4)) << 1) \
|
||||
| (((d) & (1<<5)) << 1); \
|
||||
}
|
||||
|
||||
#define read_8() ( (((GPIOA->regs->IDR & (1<<10)) >> 10) \
|
||||
| ((GPIOB->regs->IDR & (1<<7)) >> 6) \
|
||||
| ((GPIOA->regs->IDR & (1<<0)) << 2) \
|
||||
| ((GPIOA->regs->IDR & (1<<1)) << 2) \
|
||||
| ((GPIOB->regs->IDR & (1<<5)) >> 1) \
|
||||
| ((GPIOB->regs->IDR & (1<<6)) >> 1) \
|
||||
| ((GPIOA->regs->IDR & (1<<8)) >> 2) \
|
||||
| ((GPIOA->regs->IDR & (1<<9)) >> 2)))
|
||||
|
||||
// PA10,PA9,PA8 PA1,PA0 PB7,PB6,PB5
|
||||
#define setWriteDir() {GP_OUT(GPIOA, CRH, 0xFFF); GP_OUT(GPIOA, CRL, 0xFF); GP_OUT(GPIOB, CRL, 0xFFF00000); }
|
||||
#define setReadDir() {GP_INP(GPIOA, CRH, 0xFFF); GP_INP(GPIOA, CRL, 0xFF); GP_INP(GPIOB, CRL, 0xFFF00000); }
|
||||
|
||||
// MANOLO8888's wiring scheme is far simpler:
|
||||
//#define write_8(d) { GPIOA->regs->BSRR = 0x00FF << 16; GPIOA->regs->BSRR = (d) & 0xFF; }
|
||||
//#define read_8() (GPIOA->regs->IDR & 0xFF)
|
||||
// PA7 ..PA0
|
||||
//#define setWriteDir() {GP_OUT(GPIOA, CRL, 0xFFFFFFFF); }
|
||||
//#define setReadDir() {GP_INP(GPIOA, CRL, 0xFFFFFFFF); }
|
||||
|
||||
#define write8(x) { write_8(x); WR_ACTIVE; WR_STROBE; }
|
||||
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
|
||||
#define READ_8(dst) { RD_STROBE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; dst = read_8(); RD_IDLE; }
|
||||
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
|
||||
|
||||
#define PIN_HIGH(port, pin) (port)->regs->BSRR = (1<<(pin))
|
||||
//#define PIN_LOW(port, pin) (port)->regs->BSRR = (1<<((pin)+16))
|
||||
#define PIN_LOW(port, pin) (port)->regs->ODR &= ~(1<<(pin))
|
||||
#define PIN_OUTPUT(port, pin) GP_OUT(port, CRL, 0xF<<((pin)<<2)) //50MHz push-pull only 0-7
|
||||
#define PIN_INPUT(port, pin) GP_INP(port, CRL, 0xF<<((pin)<<2)) //digital input
|
||||
|
||||
#else
|
||||
#error MCU unsupported
|
||||
#endif // regular UNO shields on Arduino boards
|
||||
|
||||
#endif //!defined(USE_SPECIAL) || defined (USE_SPECIAL_FAIL)
|
||||
|
||||
#define RD_ACTIVE PIN_LOW(RD_PORT, RD_PIN)
|
||||
#define RD_IDLE PIN_HIGH(RD_PORT, RD_PIN)
|
||||
#define RD_OUTPUT PIN_OUTPUT(RD_PORT, RD_PIN)
|
||||
#define WR_ACTIVE PIN_LOW(WR_PORT, WR_PIN)
|
||||
#define WR_IDLE PIN_HIGH(WR_PORT, WR_PIN)
|
||||
#define WR_OUTPUT PIN_OUTPUT(WR_PORT, WR_PIN)
|
||||
#define CD_COMMAND PIN_LOW(CD_PORT, CD_PIN)
|
||||
#define CD_DATA PIN_HIGH(CD_PORT, CD_PIN)
|
||||
#define CD_OUTPUT PIN_OUTPUT(CD_PORT, CD_PIN)
|
||||
#define CS_ACTIVE PIN_LOW(CS_PORT, CS_PIN)
|
||||
#define CS_IDLE PIN_HIGH(CS_PORT, CS_PIN)
|
||||
#define CS_OUTPUT PIN_OUTPUT(CS_PORT, CS_PIN)
|
||||
#define RESET_ACTIVE PIN_LOW(RESET_PORT, RESET_PIN)
|
||||
#define RESET_IDLE PIN_HIGH(RESET_PORT, RESET_PIN)
|
||||
#define RESET_OUTPUT PIN_OUTPUT(RESET_PORT, RESET_PIN)
|
||||
|
||||
// General macros. IOCLR registers are 1 cycle when optimised.
|
||||
#define WR_STROBE { WR_ACTIVE; WR_IDLE; } //PWLW=TWRL=50ns
|
||||
#define RD_STROBE RD_IDLE, RD_ACTIVE, RD_ACTIVE, RD_ACTIVE //PWLR=TRDL=150ns, tDDR=100ns
|
||||
|
||||
#if defined(TEENSYDUINO)
|
||||
#warning special pinMode() initialisation for TEENSYDUINO
|
||||
#define CTL_INIT() { \
|
||||
for (int i = 2; i <= 9; i++) pinMode(i, OUTPUT); \
|
||||
for (int i = A0; i <= A4; i++) pinMode(i, OUTPUT); \
|
||||
RD_OUTPUT; WR_OUTPUT; CD_OUTPUT; CS_OUTPUT; RESET_OUTPUT; }
|
||||
#else
|
||||
#define CTL_INIT() { RD_OUTPUT; WR_OUTPUT; CD_OUTPUT; CS_OUTPUT; RESET_OUTPUT; }
|
||||
#endif
|
||||
#define WriteCmd(x) { CD_COMMAND; write16(x); }
|
||||
#define WriteData(x) { CD_DATA; write16(x); }
|
||||
851
utility/mcufriend_special.h
Normal file
851
utility/mcufriend_special.h
Normal file
@@ -0,0 +1,851 @@
|
||||
#define SSD1289_JUMPERS 2 //Uno Shield with VERY different pin-out to Mcufriend
|
||||
// only define one "USE_XXX" macro at any time
|
||||
//#define USE_SSD1289_SHIELD_UNO
|
||||
//#define USE_SSD1289_SHIELD_MEGA
|
||||
//#define USE_SSD1289_SHIELD_DUE
|
||||
//#define USE_MEGA_8BIT_PROTOSHIELD
|
||||
//#define USE_MEGA_8BIT_SHIELD
|
||||
//#define USE_MEGA_16BIT_SHIELD //RD on PL6 (D43)
|
||||
//#define USE_BLD_BST_MEGA32U4
|
||||
//#define USE_BLD_BST_MEGA2560
|
||||
//#define USE_DUE_8BIT_PROTOSHIELD
|
||||
//#define USE_DUE_16BIT_SHIELD //RD on PA15 (D24)
|
||||
//#define USE_BOBCACHELOT_TEENSY
|
||||
//#define USE_FRDM_K20
|
||||
|
||||
#if 0
|
||||
#elif defined(__AVR_ATmega328P__) && defined(USE_SSD1289_SHIELD_UNO) //on UNO
|
||||
#warning using SSD1289 Shield for mega328
|
||||
#define RD_PORT PORTC
|
||||
#define RD_PIN 3
|
||||
#define WR_PORT PORTC
|
||||
#define WR_PIN 2
|
||||
#define CD_PORT PORTC
|
||||
#define CD_PIN 1
|
||||
#define CS_PORT PORTC
|
||||
#define CS_PIN 0
|
||||
#define RESET_PORT PORTB
|
||||
#define RESET_PIN 1 //actually SD_CS
|
||||
|
||||
// SSD1289 shield has LCD_D0 on RXD0. Fine for write-only
|
||||
// For any Read operations, put jumper from D0 to D8, Switch #2 to OFF.
|
||||
// If using Serial, jumper D1 to A5, Switch #1 to OFF
|
||||
#if SSD1289_JUMPERS == 0
|
||||
#warning no jumpers. Switch #1=ON, #2=ON
|
||||
#define BMASK 0x00 //0x00 for output, 0x01 for Read + Serial
|
||||
#define CMASK 0x00 //0x20 for Read + Serial
|
||||
#define DMASK (~BMASK)
|
||||
#define write8(x) { PORTD = x; WR_STROBE; }
|
||||
#define read_8() ( PIND )
|
||||
#elif SSD1289_JUMPERS == 1
|
||||
#warning jumper D0 to D8. Switch #1=ON, #2=OFF
|
||||
#define BMASK 0x01 //0x00 for output, 0x01 for Read + Serial
|
||||
#define CMASK 0x00 //0x20 for Read + Serial
|
||||
#define DMASK (~BMASK)
|
||||
#define write8(x) { PORTD = (PORTD & ~DMASK) | (x & DMASK); PORTB = (PORTB & ~BMASK) | (x & BMASK); WR_STROBE; }
|
||||
#define read_8() ( (PIND & DMASK)|(PINB & BMASK) )
|
||||
#elif SSD1289_JUMPERS == 2
|
||||
#warning jumper D0 to D8, D1 to A5. Switch #1=OFF, #2=OFF
|
||||
#define BMASK (1<<0) //0x00 for output, 0x01 for Read + Serial
|
||||
#define CMASK (1<<5) //0x20 for Read + Serial
|
||||
#define DMASK (0xFC)
|
||||
#define write8(x) { PORTC = (PORTC & ~CMASK) | ((x<<4) & CMASK);\
|
||||
PORTD = (PORTD & ~DMASK) | (x & DMASK);\
|
||||
PORTB = (PORTB & ~BMASK) | (x & BMASK); WR_STROBE; }
|
||||
#define read_8() ( ((PINC & CMASK)>>4)|(PIND & DMASK)|(PINB & BMASK) )
|
||||
#endif
|
||||
#define setWriteDir() { DDRC |= CMASK; DDRD |= DMASK; DDRB |= BMASK; }
|
||||
#define setReadDir() { DDRC &= ~CMASK; DDRD &= ~DMASK; DDRB &= ~BMASK; }
|
||||
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
|
||||
#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
|
||||
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
|
||||
|
||||
#define PIN_LOW(p, b) (p) &= ~(1<<(b))
|
||||
#define PIN_HIGH(p, b) (p) |= (1<<(b))
|
||||
#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
|
||||
|
||||
#elif defined(__AVR_ATxmega128A1__) // Home made shield with Xplained
|
||||
#warning Home made shield with Xplained
|
||||
#define RD_PORT VPORT3
|
||||
#define RD_PIN 0
|
||||
#define WR_PORT VPORT3
|
||||
#define WR_PIN 1
|
||||
#define CD_PORT VPORT3
|
||||
#define CD_PIN 2
|
||||
#define CS_PORT VPORT3
|
||||
#define CS_PIN 3
|
||||
#define RESET_PORT VPORT3
|
||||
#define RESET_PIN 4
|
||||
|
||||
// VPORTs are very fast. CBI, SBI are only one cycle. Hence all those RD_ACTIVEs
|
||||
// ILI9320 data sheet says tDDR=100ns. We need 218ns to read REGs correctly.
|
||||
#define write_8(x) { VPORT2.OUT = x; }
|
||||
#define read_8() ( VPORT2.IN )
|
||||
#define setWriteDir() { PORTCFG.VPCTRLB=PORTCFG_VP3MAP_PORTF_gc | PORTCFG_VP2MAP_PORTC_gc; VPORT2.DIR = 0xFF; }
|
||||
#define setReadDir() { VPORT2.DIR = 0x00; }
|
||||
#define write8(x) { write_8(x); WR_STROBE; }
|
||||
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
|
||||
#define READ_8(dst) { RD_STROBE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; dst = read_8(); RD_IDLE; }
|
||||
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
|
||||
|
||||
#define PIN_LOW(p, b) (p).OUT &= ~(1<<(b))
|
||||
#define PIN_HIGH(p, b) (p).OUT |= (1<<(b))
|
||||
#define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b))
|
||||
#elif defined(__AVR_ATxmega32A4U__) // Home made shield with Batsocks module
|
||||
#warning Home made shield with Batsocks module
|
||||
#define RD_PORT VPORT3
|
||||
#define RD_PIN 0
|
||||
#define WR_PORT VPORT3
|
||||
#define WR_PIN 1
|
||||
#define CD_PORT VPORT3
|
||||
#define CD_PIN 2
|
||||
#define CS_PORT VPORT3
|
||||
#define CS_PIN 3
|
||||
#define RESET_PORT PORTE
|
||||
#define RESET_PIN 0
|
||||
|
||||
// VPORTs are very fast. CBI, SBI are only one cycle. Hence all those RD_ACTIVEs
|
||||
// ILI9320 data sheet says tDDR=100ns. We need 218ns to read REGs correctly.
|
||||
// S6D0154 data sheet says tDDR=250ns. We need ~500ns to read REGs correctly.
|
||||
#define write_8(x) { VPORT2.OUT = x; }
|
||||
#define read_8() ( VPORT2.IN )
|
||||
#define setWriteDir() { PORTCFG.VPCTRLB=PORTCFG_VP13MAP_PORTB_gc | PORTCFG_VP02MAP_PORTC_gc; VPORT2.DIR = 0xFF; }
|
||||
#define setReadDir() { VPORT2.DIR = 0x00; }
|
||||
#define write8(x) { write_8(x); WR_STROBE; }
|
||||
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
|
||||
#define READ_8(dst) { RD_STROBE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; dst = read_8(); RD_IDLE; }
|
||||
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
|
||||
|
||||
#define PIN_LOW(p, b) (p).OUT &= ~(1<<(b))
|
||||
#define PIN_HIGH(p, b) (p).OUT |= (1<<(b))
|
||||
#define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b))
|
||||
|
||||
#elif defined(__AVR_ATmega2560__) && defined(USE_BLD_BST_MEGA2560) //regular UNO shield on MEGA2560 using BLD/BST
|
||||
#warning regular UNO shield on MEGA2560 using BLD/BST
|
||||
#define RD_PORT PORTF
|
||||
#define RD_PIN 0
|
||||
#define WR_PORT PORTF
|
||||
#define WR_PIN 1
|
||||
#define CD_PORT PORTF
|
||||
#define CD_PIN 2
|
||||
#define CS_PORT PORTF
|
||||
#define CS_PIN 3
|
||||
#define RESET_PORT PORTF
|
||||
#define RESET_PIN 4
|
||||
|
||||
#define EMASK 0x38
|
||||
#define GMASK 0x20
|
||||
#define HMASK 0x78
|
||||
static inline void write_8(uint8_t val)
|
||||
{
|
||||
asm volatile("lds __tmp_reg__,0x0102" "\n\t"
|
||||
"BST %0,0" "\n\t" "BLD __tmp_reg__,5" "\n\t"
|
||||
"BST %0,1" "\n\t" "BLD __tmp_reg__,6" "\n\t"
|
||||
"BST %0,6" "\n\t" "BLD __tmp_reg__,3" "\n\t"
|
||||
"BST %0,7" "\n\t" "BLD __tmp_reg__,4" "\n\t"
|
||||
"sts 0x0102,__tmp_reg__" : : "a" (val));
|
||||
asm volatile("in __tmp_reg__,0x0E" "\n\t"
|
||||
"BST %0,2" "\n\t" "BLD __tmp_reg__,4" "\n\t"
|
||||
"BST %0,3" "\n\t" "BLD __tmp_reg__,5" "\n\t"
|
||||
"BST %0,5" "\n\t" "BLD __tmp_reg__,3" "\n\t"
|
||||
"out 0x0E,__tmp_reg__" : : "a" (val));
|
||||
asm volatile("in __tmp_reg__,0x14" "\n\t"
|
||||
"BST %0,4" "\n\t" "BLD __tmp_reg__,5" "\n\t"
|
||||
"out 0x14,__tmp_reg__" : : "a" (val));
|
||||
}
|
||||
|
||||
#define read_8() ( ((PINH & (3<<5)) >> 5)\
|
||||
| ((PINE & (3<<4)) >> 2)\
|
||||
| ((PING & (1<<5)) >> 1)\
|
||||
| ((PINE & (1<<3)) << 2)\
|
||||
| ((PINH & (3<<3)) << 3)\
|
||||
)
|
||||
#define setWriteDir() { DDRH |= HMASK; DDRG |= GMASK; DDRE |= EMASK; }
|
||||
#define setReadDir() { DDRH &= ~HMASK; DDRG &= ~GMASK; DDRE &= ~EMASK; }
|
||||
#define write8(x) { write_8(x); WR_STROBE; }
|
||||
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
|
||||
#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
|
||||
#define READ_16(dst) { RD_STROBE; dst = read_8(); RD_IDLE; RD_STROBE; dst = (dst<<8) | read_8(); RD_IDLE; }
|
||||
|
||||
#define PIN_LOW(p, b) (p) &= ~(1<<(b))
|
||||
#define PIN_HIGH(p, b) (p) |= (1<<(b))
|
||||
#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
|
||||
|
||||
#elif defined(__AVR_ATmega2560__) && defined(USE_SSD1289_SHIELD_MEGA) //on MEGA2560
|
||||
#warning using SSD1289 Shield for mega2560
|
||||
#define RD_PORT PORTF
|
||||
#define RD_PIN 3 //A3
|
||||
#define WR_PORT PORTF
|
||||
#define WR_PIN 2 //A2
|
||||
#define CD_PORT PORTF
|
||||
#define CD_PIN 1 //A1
|
||||
#define CS_PORT PORTF
|
||||
#define CS_PIN 0 //A0
|
||||
#define RESET_PORT PORTH
|
||||
#define RESET_PIN 6 //D9 DS_CS, D10=T_CS, D9=SD_CS, D8=n.c.
|
||||
|
||||
// only for SSD1289 data bus on D2..D9 UNTESTED
|
||||
#if (SSD1289_JUMPERS == 0) //Switch #1=ON, #2=ON
|
||||
#warning no jumpers Switch #1=ON, #2=ON
|
||||
#define EMASK 0x3B
|
||||
#define FMASK 0x00
|
||||
#define HMASK 0x18
|
||||
#define GMASK 0x20
|
||||
#define write_8(x) { PORTH &= ~HMASK; PORTG &= ~GMASK; PORTE &= ~EMASK; \
|
||||
PORTE |= (((x) & (1<<0)) << 0); \
|
||||
PORTE |= (((x) & (1<<1)) << 0); \
|
||||
PORTE |= (((x) & (3<<2)) << 2); \
|
||||
PORTG |= (((x) & (1<<4)) << 1); \
|
||||
PORTE |= (((x) & (1<<5)) >> 2); \
|
||||
PORTH |= (((x) & (3<<6)) >> 3); \
|
||||
}
|
||||
|
||||
#define read_8() ( ((PINE & (1<<0)) >> 0)\
|
||||
| ((PINE & (1<<1)) >> 0)\
|
||||
| ((PINE & (3<<4)) >> 2)\
|
||||
| ((PING & (1<<5)) >> 1)\
|
||||
| ((PINE & (1<<3)) << 2)\
|
||||
| ((PINH & (3<<3)) << 3)\
|
||||
)
|
||||
#elif (SSD1289_JUMPERS == 1) //jumper D0 to D8. Switch #1=ON, #2=OFF
|
||||
#warning jumper D0 to D8. Switch #1=ON, #2=OFF
|
||||
#define EMASK 0x3A
|
||||
#define FMASK 0x00
|
||||
#define HMASK 0x38
|
||||
#define GMASK 0x20
|
||||
#define write_8(x) { PORTH &= ~HMASK; PORTG &= ~GMASK; PORTE &= ~EMASK; \
|
||||
PORTH |= (((x) & (1<<0)) << 5); \
|
||||
PORTE |= (((x) & (1<<1)) << 0); \
|
||||
PORTE |= (((x) & (3<<2)) << 2); \
|
||||
PORTG |= (((x) & (1<<4)) << 1); \
|
||||
PORTE |= (((x) & (1<<5)) >> 2); \
|
||||
PORTH |= (((x) & (3<<6)) >> 3); \
|
||||
}
|
||||
|
||||
#define read_8() ( ((PINH & (1<<5)) >> 5)\
|
||||
| ((PINE & (1<<1)) >> 0)\
|
||||
| ((PINE & (3<<4)) >> 2)\
|
||||
| ((PING & (1<<5)) >> 1)\
|
||||
| ((PINE & (1<<3)) << 2)\
|
||||
| ((PINH & (3<<3)) << 3)\
|
||||
)
|
||||
#elif (SSD1289_JUMPERS == 2) //jumper D0 to D8, D1 to A5. Switch #1=OFF, #2=OFF
|
||||
#warning jumper D0 to D8, D1 to A5. Switch #1=OFF, #2=OFF
|
||||
#define FMASK 0x20
|
||||
#define EMASK 0x38
|
||||
#define HMASK 0x38
|
||||
#define GMASK 0x20
|
||||
#define write_8(x) { PORTH &= ~HMASK; PORTG &= ~GMASK; PORTF &= ~FMASK; PORTE &= ~EMASK; \
|
||||
PORTH |= (((x) & (1<<0)) << 5); \
|
||||
PORTF |= (((x) & (1<<1)) << 4); \
|
||||
PORTE |= (((x) & (3<<2)) << 2); \
|
||||
PORTG |= (((x) & (1<<4)) << 1); \
|
||||
PORTE |= (((x) & (1<<5)) >> 2); \
|
||||
PORTH |= (((x) & (3<<6)) >> 3); \
|
||||
}
|
||||
|
||||
#define read_8() ( ((PINH & (1<<5)) >> 5)\
|
||||
| ((PINF & (1<<5)) >> 4)\
|
||||
| ((PINE & (3<<4)) >> 2)\
|
||||
| ((PING & (1<<5)) >> 1)\
|
||||
| ((PINE & (1<<3)) << 2)\
|
||||
| ((PINH & (3<<3)) << 3)\
|
||||
)
|
||||
#endif
|
||||
#define setWriteDir() { DDRH |= HMASK; DDRG |= GMASK; DDRF |= FMASK; DDRE |= EMASK; }
|
||||
#define setReadDir() { DDRH &= ~HMASK; DDRG &= ~GMASK; DDRF &= ~FMASK; DDRE &= ~EMASK; }
|
||||
#define write8(x) { write_8(x); WR_STROBE; }
|
||||
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
|
||||
#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
|
||||
#define READ_16(dst) { RD_STROBE; dst = read_8(); RD_IDLE; RD_STROBE; dst = (dst<<8) | read_8(); RD_IDLE; }
|
||||
|
||||
#define PIN_LOW(p, b) (p) &= ~(1<<(b))
|
||||
#define PIN_HIGH(p, b) (p) |= (1<<(b))
|
||||
#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
|
||||
|
||||
#elif defined(__AVR_ATmega2560__) && defined(USE_MEGA_16BIT_SHIELD)
|
||||
#warning USE_MEGA_16BIT_SHIELD
|
||||
#define RD_PORT PORTL
|
||||
#define RD_PIN 6 //PL6 (D43). Graham has PA15 (D24) on Due Shield
|
||||
#define WR_PORT PORTG
|
||||
#define WR_PIN 2 //D39 CTE
|
||||
#define CD_PORT PORTD
|
||||
#define CD_PIN 7 //D38 CTE
|
||||
#define CS_PORT PORTG
|
||||
#define CS_PIN 1 //D40 CTE
|
||||
#define RESET_PORT PORTG
|
||||
#define RESET_PIN 0 //D41 CTE
|
||||
|
||||
#define write_8(x) { PORTC = x; }
|
||||
#define write_16(x) { PORTA = (x) >> 8; PORTC = x; }
|
||||
|
||||
#define read_16() ( (PINA<<8) | (PINC) )
|
||||
#define setWriteDir() { DDRC = 0xFF; DDRA = 0xff; }
|
||||
#define setReadDir() { DDRC = 0x00; DDRA = 0x00; }
|
||||
#define write8(x) { write_8(x); WR_STROBE; }
|
||||
#define write16(x) { write_16(x); WR_STROBE; }
|
||||
#define READ_16(dst) { RD_STROBE; dst = read_16(); RD_IDLE; }
|
||||
#define READ_8(dst) { READ_16(dst); dst &= 0xFFFF; }
|
||||
|
||||
#define PIN_LOW(p, b) (p) &= ~(1<<(b))
|
||||
#define PIN_HIGH(p, b) (p) |= (1<<(b))
|
||||
#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
|
||||
|
||||
#elif defined(__AVR_ATmega2560__) && defined(USE_MEGA_8BIT_SHIELD)
|
||||
#warning USE_MEGA_8BIT_SHIELD for vagos21
|
||||
#define RD_PORT PORTL
|
||||
#define RD_PIN 6 //PL6 (D43). Graham has PA15 (D24) on Due Shield
|
||||
#define WR_PORT PORTG
|
||||
#define WR_PIN 2 //D39 CTE
|
||||
#define CD_PORT PORTD
|
||||
#define CD_PIN 7 //D38 CTE
|
||||
#define CS_PORT PORTG
|
||||
#define CS_PIN 1 //D40 CTE
|
||||
#define RESET_PORT PORTG
|
||||
#define RESET_PIN 0 //D41 CTE
|
||||
|
||||
#define write_8(x) { PORTA = x;}
|
||||
|
||||
#define read_8() ( PINA )
|
||||
#define setWriteDir() { DDRA = 0xFF; }
|
||||
#define setReadDir() { DDRA = 0x00; }
|
||||
#define write8(x) { write_8(x); WR_STROBE; }
|
||||
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
|
||||
#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
|
||||
#define READ_16(dst) { RD_STROBE; dst = read_8(); RD_IDLE; RD_STROBE; dst = (dst<<8) | read_8(); RD_IDLE; }
|
||||
|
||||
#define PIN_LOW(p, b) (p) &= ~(1<<(b))
|
||||
#define PIN_HIGH(p, b) (p) |= (1<<(b))
|
||||
#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
|
||||
|
||||
#elif defined(__AVR_ATmega2560__) && defined(USE_MEGA_8BIT_PROTOSHIELD)
|
||||
#warning USE_MEGA_8BIT_PROTOSHIELD
|
||||
#define RD_PORT PORTF
|
||||
#define RD_PIN 0
|
||||
#define WR_PORT PORTF
|
||||
#define WR_PIN 1
|
||||
#define CD_PORT PORTF
|
||||
#define CD_PIN 2
|
||||
#define CS_PORT PORTF
|
||||
#define CS_PIN 3
|
||||
#define RESET_PORT PORTF
|
||||
#define RESET_PIN 4
|
||||
|
||||
#define write_8(x) { PORTA = x;}
|
||||
|
||||
#define read_8() ( PINA )
|
||||
#define setWriteDir() { DDRA = 0xFF; }
|
||||
#define setReadDir() { DDRA = 0x00; }
|
||||
#define write8(x) { write_8(x); WR_STROBE; }
|
||||
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
|
||||
#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
|
||||
#define READ_16(dst) { RD_STROBE; dst = read_8(); RD_IDLE; RD_STROBE; dst = (dst<<8) | read_8(); RD_IDLE; }
|
||||
|
||||
#define PIN_LOW(p, b) (p) &= ~(1<<(b))
|
||||
#define PIN_HIGH(p, b) (p) |= (1<<(b))
|
||||
#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
|
||||
|
||||
#elif defined(__AVR_ATmega32U4__) && defined(USE_BLD_BST_MEGA32U4) //regular UNO shield on Leonardo using BST/BLD
|
||||
#warning regular UNO shield on Leonardo using BST/BLD
|
||||
#define RD_PORT PORTF
|
||||
#define RD_PIN 7
|
||||
#define WR_PORT PORTF
|
||||
#define WR_PIN 6
|
||||
#define CD_PORT PORTF
|
||||
#define CD_PIN 5
|
||||
#define CS_PORT PORTF
|
||||
#define CS_PIN 4
|
||||
#define RESET_PORT PORTF
|
||||
#define RESET_PIN 1
|
||||
|
||||
#define BMASK (3<<4)
|
||||
#define CMASK (1<<6)
|
||||
#define DMASK ((1<<7)|(1<<4)|(3<<0))
|
||||
#define EMASK (1<<6)
|
||||
static inline void write_8(uint8_t val)
|
||||
{
|
||||
asm volatile("in __tmp_reg__,0x05" "\n\t"
|
||||
"BST %0,0" "\n\t" "BLD __tmp_reg__,4" "\n\t"
|
||||
"BST %0,1" "\n\t" "BLD __tmp_reg__,5" "\n\t"
|
||||
"out 0x05,__tmp_reg__" : : "a" (val));
|
||||
asm volatile("in __tmp_reg__,0x0B" "\n\t"
|
||||
"BST %0,2" "\n\t" "BLD __tmp_reg__,1" "\n\t"
|
||||
"BST %0,3" "\n\t" "BLD __tmp_reg__,0" "\n\t"
|
||||
"BST %0,4" "\n\t" "BLD __tmp_reg__,4" "\n\t"
|
||||
"BST %0,6" "\n\t" "BLD __tmp_reg__,7" "\n\t"
|
||||
"out 0x0B,__tmp_reg__" : : "a" (val));
|
||||
asm volatile("in __tmp_reg__,0x08" "\n\t"
|
||||
"BST %0,5" "\n\t" "BLD __tmp_reg__,6" "\n\t"
|
||||
"out 0x08,__tmp_reg__" : : "a" (val));
|
||||
asm volatile("in __tmp_reg__,0x0E" "\n\t"
|
||||
"BST %0,7" "\n\t" "BLD __tmp_reg__,6" "\n\t"
|
||||
"out 0x0E,__tmp_reg__" : : "a" (val));
|
||||
}
|
||||
#define read_8() ( ((PINB & (3<<4)) >> 4)\
|
||||
| ((PIND & (1<<1)) << 1)\
|
||||
| ((PIND & (1<<0)) << 3)\
|
||||
| ((PIND & (1<<4)) >> 0)\
|
||||
| ((PINC & (1<<6)) >> 1)\
|
||||
| ((PIND & (1<<7)) >> 1)\
|
||||
| ((PINE & (1<<6)) << 1)\
|
||||
)
|
||||
#define setWriteDir() { DDRB |= BMASK; DDRC |= CMASK; DDRD |= DMASK; DDRE |= EMASK; }
|
||||
#define setReadDir() { DDRB &= ~BMASK; DDRC &= ~CMASK; DDRD &= ~DMASK; DDRE &= ~EMASK; }
|
||||
#define write8(x) { write_8(x); WR_STROBE; }
|
||||
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
|
||||
#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
|
||||
#define READ_16(dst) { RD_STROBE; dst = read_8(); RD_IDLE; RD_STROBE; dst = (dst<<8) | read_8(); RD_IDLE; }
|
||||
|
||||
#define PIN_LOW(p, b) (p) &= ~(1<<(b))
|
||||
#define PIN_HIGH(p, b) (p) |= (1<<(b))
|
||||
#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
|
||||
|
||||
#elif defined(__SAMD21J18A__) //regular UNO shield on D21_XPRO
|
||||
#warning regular UNO shield on D21_XPRO
|
||||
#include "samd21.h"
|
||||
// configure macros for the control pins
|
||||
#define RD_PORT PORT->Group[1]
|
||||
#define RD_PIN 0
|
||||
#define WR_PORT PORT->Group[1]
|
||||
#define WR_PIN 1
|
||||
#define CD_PORT PORT->Group[0]
|
||||
#define CD_PIN 10
|
||||
#define CS_PORT PORT->Group[0]
|
||||
#define CS_PIN 11
|
||||
#define RESET_PORT PORT->Group[0]
|
||||
#define RESET_PIN 8
|
||||
// configure macros for data bus
|
||||
#define AMASK 0x00220000
|
||||
#define BMASK 0x0000C0E4
|
||||
#define write_8(d) { \
|
||||
PORT->Group[0].OUT.reg = (PORT->Group[0].OUT.reg & ~AMASK) \
|
||||
| (((d) & (1<<5)) << 16) \
|
||||
| (((d) & (1<<7)) << 10); \
|
||||
PORT->Group[1].OUT.reg = (PORT->Group[1].OUT.reg & ~BMASK) \
|
||||
| (((d) & (3<<0)) << 6) \
|
||||
| (((d) & (1<<2)) << 12) \
|
||||
| (((d) & (1<<3)) >> 1) \
|
||||
| (((d) & (1<<4)) << 1) \
|
||||
| (((d) & (1<<6)) << 9); \
|
||||
}
|
||||
#define read_8() ( (((PORT->Group[0].IN.reg & (1<<21)) >> 16) \
|
||||
| ((PORT->Group[0].IN.reg & (1<<17)) >> 10) \
|
||||
| ((PORT->Group[1].IN.reg & (3<<6)) >> 6) \
|
||||
| ((PORT->Group[1].IN.reg & (1<<14)) >> 12) \
|
||||
| ((PORT->Group[1].IN.reg & (1<<2)) << 1) \
|
||||
| ((PORT->Group[1].IN.reg & (1<<5)) >> 1) \
|
||||
| ((PORT->Group[1].IN.reg & (1<<15)) >> 9)))
|
||||
#define setWriteDir() { \
|
||||
PORT->Group[0].DIRSET.reg = AMASK; \
|
||||
PORT->Group[1].DIRSET.reg = BMASK; \
|
||||
PORT->Group[0].WRCONFIG.reg = (AMASK>>16) | (0<<22) | (0<<28) | (1<<30) | (1<<31); \
|
||||
PORT->Group[1].WRCONFIG.reg = (BMASK & 0xFFFF) | (0<<22) | (0<<28) | (1<<30); \
|
||||
}
|
||||
#define setReadDir() { \
|
||||
PORT->Group[0].DIRCLR.reg = AMASK; \
|
||||
PORT->Group[1].DIRCLR.reg = BMASK; \
|
||||
PORT->Group[0].WRCONFIG.reg = (AMASK>>16) | (1<<17) | (0<<28) | (1<<30) | (1<<31); \
|
||||
PORT->Group[1].WRCONFIG.reg = (BMASK & 0xFFFF) | (1<<17) | (0<<28) | (1<<30); \
|
||||
}
|
||||
|
||||
#define write8(x) { write_8(x); WR_STROBE; }
|
||||
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
|
||||
#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
|
||||
#define READ_16(dst) { RD_STROBE; dst = read_8(); RD_IDLE; RD_STROBE; dst = (dst<<8) | read_8(); RD_IDLE; }
|
||||
// Shield Control macros.
|
||||
#define PIN_LOW(port, pin) (port).OUTCLR.reg = (1<<(pin))
|
||||
#define PIN_HIGH(port, pin) (port).OUTSET.reg = (1<<(pin))
|
||||
#define PIN_OUTPUT(port, pin) (port).DIR.reg |= (1<<(pin))
|
||||
|
||||
#elif defined(__SAM3X8E__) && defined(USE_SSD1289_SHIELD_DUE) // on DUE
|
||||
#warning USE_SSD1289_SHIELD_DUE
|
||||
// configure macros for the control pins
|
||||
#define RD_PORT PIOA
|
||||
#define RD_PIN 22 //A3
|
||||
#define WR_PORT PIOA
|
||||
#define WR_PIN 23 //A2
|
||||
#define CD_PORT PIOA
|
||||
#define CD_PIN 24 //A1
|
||||
#define CS_PORT PIOA
|
||||
#define CS_PIN 16 //A0
|
||||
#define RESET_PORT PIOC
|
||||
#define RESET_PIN 21 //D9 Touch CS
|
||||
// configure macros for data bus
|
||||
// only for SSD1289 data bus on D2..D9 UNTESTED
|
||||
#if SSD1289_JUMPERS == 0
|
||||
#warning no jumpers Switch #1=ON, #2=ON
|
||||
#define AMASK (3<<8)
|
||||
#define BMASK (1<<25)
|
||||
#define CMASK (0xBC << 21)
|
||||
#define write_8(x) { PIOA->PIO_CODR = AMASK; PIOB->PIO_CODR = BMASK; PIOC->PIO_CODR = CMASK; \
|
||||
PIOA->PIO_SODR = (((x) & (1<<0)) << 8); \
|
||||
PIOA->PIO_SODR = (((x) & (1<<1)) << 8); \
|
||||
PIOB->PIO_SODR = (((x) & (1<<2)) << 23); \
|
||||
PIOC->PIO_SODR = (((x) & (1<<3)) << 25); \
|
||||
PIOC->PIO_SODR = (((x) & (1<<4)) << 22); \
|
||||
PIOC->PIO_SODR = (((x) & (1<<5)) << 20); \
|
||||
PIOC->PIO_SODR = (((x) & (1<<6)) << 18); \
|
||||
PIOC->PIO_SODR = (((x) & (1<<7)) << 16); \
|
||||
}
|
||||
|
||||
#define read_8() ( ((PIOA->PIO_PDSR & (1<<8)) >> 8)\
|
||||
| ((PIOA->PIO_PDSR & (1<<9)) >> 8)\
|
||||
| ((PIOB->PIO_PDSR & (1<<25)) >> 23)\
|
||||
| ((PIOC->PIO_PDSR & (1<<28)) >> 25)\
|
||||
| ((PIOC->PIO_PDSR & (1<<26)) >> 22)\
|
||||
| ((PIOC->PIO_PDSR & (1<<25)) >> 20)\
|
||||
| ((PIOC->PIO_PDSR & (1<<24)) >> 18)\
|
||||
| ((PIOC->PIO_PDSR & (1<<23)) >> 16)\
|
||||
)
|
||||
#elif SSD1289_JUMPERS == 1
|
||||
#warning jumper D0 to D8. Switch #1=ON, #2=OFF
|
||||
#define AMASK (1<<9)
|
||||
#define BMASK (1<<25)
|
||||
#define CMASK (0xBE << 21)
|
||||
#define write_8(x) { PIOA->PIO_CODR = AMASK; PIOB->PIO_CODR = BMASK; PIOC->PIO_CODR = CMASK; \
|
||||
PIOC->PIO_SODR = (((x) & (1<<0)) << 22); \
|
||||
PIOA->PIO_SODR = (((x) & (1<<1)) << 8); \
|
||||
PIOB->PIO_SODR = (((x) & (1<<2)) << 23); \
|
||||
PIOC->PIO_SODR = (((x) & (1<<3)) << 25); \
|
||||
PIOC->PIO_SODR = (((x) & (1<<4)) << 22); \
|
||||
PIOC->PIO_SODR = (((x) & (1<<5)) << 20); \
|
||||
PIOC->PIO_SODR = (((x) & (1<<6)) << 18); \
|
||||
PIOC->PIO_SODR = (((x) & (1<<7)) << 16); \
|
||||
}
|
||||
|
||||
#define read_8() ( ((PIOC->PIO_PDSR & (1<<22)) >> 22)\
|
||||
| ((PIOA->PIO_PDSR & (1<<9)) >> 8)\
|
||||
| ((PIOB->PIO_PDSR & (1<<25)) >> 23)\
|
||||
| ((PIOC->PIO_PDSR & (1<<28)) >> 25)\
|
||||
| ((PIOC->PIO_PDSR & (1<<26)) >> 22)\
|
||||
| ((PIOC->PIO_PDSR & (1<<25)) >> 20)\
|
||||
| ((PIOC->PIO_PDSR & (1<<24)) >> 18)\
|
||||
| ((PIOC->PIO_PDSR & (1<<23)) >> 16)\
|
||||
)
|
||||
#elif SSD1289_JUMPERS == 2
|
||||
#warning jumper D0 to D8, D1 to A5. Switch #1=OFF, #2=OFF
|
||||
#define AMASK (1<<4)
|
||||
#define BMASK (1<<25)
|
||||
#define CMASK (0xBE << 21)
|
||||
#define write_8(x) { PIOA->PIO_CODR = AMASK; PIOB->PIO_CODR = BMASK; PIOC->PIO_CODR = CMASK; \
|
||||
PIOC->PIO_SODR = (((x) & (1<<0)) << 22); \
|
||||
PIOA->PIO_SODR = (((x) & (1<<1)) << 3); \
|
||||
PIOB->PIO_SODR = (((x) & (1<<2)) << 23); \
|
||||
PIOC->PIO_SODR = (((x) & (1<<3)) << 25); \
|
||||
PIOC->PIO_SODR = (((x) & (1<<4)) << 22); \
|
||||
PIOC->PIO_SODR = (((x) & (1<<5)) << 20); \
|
||||
PIOC->PIO_SODR = (((x) & (1<<6)) << 18); \
|
||||
PIOC->PIO_SODR = (((x) & (1<<7)) << 16); \
|
||||
}
|
||||
|
||||
#define read_8() ( ((PIOC->PIO_PDSR & (1<<22)) >> 22)\
|
||||
| ((PIOA->PIO_PDSR & (1<<4)) >> 3)\
|
||||
| ((PIOB->PIO_PDSR & (1<<25)) >> 23)\
|
||||
| ((PIOC->PIO_PDSR & (1<<28)) >> 25)\
|
||||
| ((PIOC->PIO_PDSR & (1<<26)) >> 22)\
|
||||
| ((PIOC->PIO_PDSR & (1<<25)) >> 20)\
|
||||
| ((PIOC->PIO_PDSR & (1<<24)) >> 18)\
|
||||
| ((PIOC->PIO_PDSR & (1<<23)) >> 16)\
|
||||
)
|
||||
#endif
|
||||
#define setWriteDir() { PIOA->PIO_OER = AMASK; PIOB->PIO_OER = BMASK; PIOC->PIO_OER = CMASK; }
|
||||
#define setReadDir() { \
|
||||
PMC->PMC_PCER0 = (1 << ID_PIOA)|(1 << ID_PIOB)|(1 << ID_PIOC);\
|
||||
PIOA->PIO_ODR = AMASK; PIOB->PIO_ODR = BMASK; PIOC->PIO_ODR = CMASK;\
|
||||
}
|
||||
#define write8(x) { write_8(x); WR_ACTIVE; WR_STROBE; WR_IDLE; }
|
||||
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
|
||||
#define READ_8(dst) { RD_STROBE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; dst = read_8(); RD_IDLE; RD_IDLE; RD_IDLE; }
|
||||
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
|
||||
// Shield Control macros.
|
||||
#define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin))
|
||||
#define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin))
|
||||
#define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin))
|
||||
|
||||
#elif defined(__SAM3X8E__) && defined(USE_DUE_8BIT_PROTOSHIELD) //regular UNO shield on DUE
|
||||
#warning USE_DUE_8BIT_PROTOSHIELD
|
||||
// configure macros for the control pins
|
||||
#define RD_PORT PIOA
|
||||
#define RD_PIN 16 //A0
|
||||
#define WR_PORT PIOA
|
||||
#define WR_PIN 24 //A1
|
||||
#define CD_PORT PIOA
|
||||
#define CD_PIN 23 //A2
|
||||
#define CS_PORT PIOA
|
||||
#define CS_PIN 22 //A3
|
||||
#define RESET_PORT PIOA
|
||||
#define RESET_PIN 6 //A4
|
||||
// configure macros for data bus
|
||||
#define DMASK (0xFF<<0)
|
||||
#define write_8(x) { PIOD->PIO_CODR = DMASK; PIOD->PIO_SODR = x; }
|
||||
|
||||
#define read_8() ( PIOD->PIO_PDSR & DMASK)
|
||||
#define setWriteDir() { PIOD->PIO_OER = DMASK; PIOD->PIO_PER = DMASK; }
|
||||
#define setReadDir() { PMC->PMC_PCER0 = (1 << ID_PIOD); PIOD->PIO_ODR = DMASK;}
|
||||
#define write8(x) { write_8(x); WR_ACTIVE; WR_STROBE; WR_IDLE; WR_IDLE; }
|
||||
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
|
||||
#define READ_8(dst) { RD_STROBE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; dst = read_8(); RD_IDLE; RD_IDLE; RD_IDLE; }
|
||||
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
|
||||
// Shield Control macros.
|
||||
#define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin))
|
||||
#define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin))
|
||||
#define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin))
|
||||
|
||||
#elif defined(__SAM3X8E__) && defined(USE_DUE_16BIT_SHIELD) //regular CTE shield on DUE
|
||||
#warning USE_DUE_16BIT_SHIELD
|
||||
// configure macros for the control pins
|
||||
#define RD_PORT PIOA
|
||||
#define RD_PIN 15 //D24 Graham
|
||||
#define WR_PORT PIOD
|
||||
#define WR_PIN 1 //D26
|
||||
#define CD_PORT PIOD
|
||||
#define CD_PIN 0 //D25
|
||||
#define CS_PORT PIOD
|
||||
#define CS_PIN 2 //D27
|
||||
#define RESET_PORT PIOD
|
||||
#define RESET_PIN 3 //D28
|
||||
// configure macros for data bus
|
||||
// DB0..DB7 on PIOC1..PIOC8, DB8..DB15 on PIOC12..PIOC19
|
||||
//
|
||||
#define CMASKH (0xFF00<<4)
|
||||
#define CMASKL (0x00FF<<1)
|
||||
#define CMASK (CMASKH | CMASKL)
|
||||
#define write_8(x) { PIOC->PIO_CODR = CMASKL; PIOC->PIO_SODR = (((x)&0x00FF)<<1); }
|
||||
#define write_16(x) { PIOC->PIO_CODR = CMASK; \
|
||||
PIOC->PIO_SODR = (((x)&0x00FF)<<1)|(((x)&0xFF00)<<4); }
|
||||
#define read_16() (((PIOC->PIO_PDSR & CMASKH)>>4)|((PIOC->PIO_PDSR & CMASKL)>>1) )
|
||||
#define read_8() (read_16() & 0xFF)
|
||||
#define setWriteDir() { PIOC->PIO_OER = CMASK; PIOC->PIO_PER = CMASK; }
|
||||
#define setReadDir() { PMC->PMC_PCER0 = (1 << ID_PIOC); PIOC->PIO_ODR = CMASK; }
|
||||
#define write8(x) { write16(x & 0xFF); }
|
||||
#define write16(x) { write_16(x); WR_ACTIVE; WR_STROBE; WR_IDLE; WR_IDLE; }
|
||||
#define READ_16(dst) { RD_STROBE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; dst = read_16(); RD_IDLE; RD_IDLE; RD_IDLE; }
|
||||
#define READ_8(dst) { READ_16(dst); dst &= 0xFF; }
|
||||
|
||||
// Shield Control macros.
|
||||
#define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin))
|
||||
#define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin))
|
||||
#define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin))
|
||||
|
||||
#elif defined(__SAM3X8E__) && defined(USE_MEGA_16BIT_SHIELD) //regular CTE shield on DUE
|
||||
#warning USE_MEGA_16BIT_SHIELD
|
||||
// configure macros for the control pins
|
||||
#define RD_PORT PIOA
|
||||
#define RD_PIN 20 //D43
|
||||
#define WR_PORT PIOC
|
||||
#define WR_PIN 7 //D39
|
||||
#define CD_PORT PIOC
|
||||
#define CD_PIN 6 //D38
|
||||
#define CS_PORT PIOC
|
||||
#define CS_PIN 8 //D40
|
||||
#define RESET_PORT PIOC
|
||||
#define RESET_PIN 9 //D41
|
||||
// configure macros for data bus
|
||||
//
|
||||
#define AMASK ((1<<7)|(3<<14)) //PA7, PA14-PA15
|
||||
#define BMASK (1<<26) //PB26
|
||||
#define CMASK (31<<1) //PC1-PC5
|
||||
#define DMASK ((15<<0)|(1<<6)|(3<<9)) //PD0-PD3, PD6, PD9-PD10
|
||||
|
||||
#define write_16(x) { PIOA->PIO_CODR = AMASK; PIOB->PIO_CODR = BMASK; PIOC->PIO_CODR = CMASK; PIOD->PIO_CODR = DMASK; \
|
||||
PIOA->PIO_SODR = (((x)&(1<<6))<<1)|(((x)&(3<<9))<<5); \
|
||||
PIOB->PIO_SODR = (((x)&(1<<8))<<18); \
|
||||
PIOC->PIO_SODR = (((x)&(1<<0))<<5); \
|
||||
PIOC->PIO_SODR = (((x)&(1<<1))<<3); \
|
||||
PIOC->PIO_SODR = (((x)&(1<<2))<<1); \
|
||||
PIOC->PIO_SODR = (((x)&(1<<3))>>1); \
|
||||
PIOC->PIO_SODR = (((x)&(1<<4))>>3); \
|
||||
PIOD->PIO_SODR = (((x)&(1<<7))<<2)|(((x)&(1<<5))<<5)|(((x)&(15<<11))>>11)|(((x)&(1<<15))>>9); \
|
||||
}
|
||||
|
||||
/*
|
||||
#define write_16(VL) { PIOA->PIO_CODR = AMASK; PIOC->PIO_CODR = CMASK; PIOD->PIO_CODR = DMASK; \
|
||||
REG_PIOA_SODR=((((VL)>>8) & 0x06)<<13) | ((VL & 0x40)<<1);\
|
||||
if ((VL)&(1<<8)) REG_PIOB_SODR=(1<<26); else REG_PIOB_CODR=(1<<26);\
|
||||
REG_PIOC_SODR=((VL & 0x01)<<5) | ((VL & 0x02)<<3) | ((VL & 0x04)<<1) | ((VL & 0x08)>>1) | ((VL & 0x10)>>3);\
|
||||
REG_PIOD_SODR=((((VL)>>8) & 0x78)>>3) | ((((VL)>>8) & 0x80)>>1) | ((VL & 0x20)<<5) | ((VL & 0x80)<<2);\
|
||||
}
|
||||
*/
|
||||
#define read_16() ( 0\
|
||||
|((PIOC->PIO_PDSR & (1<<5))>>5)\
|
||||
|((PIOC->PIO_PDSR & (1<<4))>>3)\
|
||||
|((PIOC->PIO_PDSR & (1<<3))>>1)\
|
||||
|((PIOC->PIO_PDSR & (1<<2))<<1)\
|
||||
|((PIOC->PIO_PDSR & (1<<1))<<3)\
|
||||
|((PIOD->PIO_PDSR & (1<<10))>>5)\
|
||||
|((PIOA->PIO_PDSR & (1<<7))>>1)\
|
||||
|((PIOD->PIO_PDSR & (1<<9))>>2)\
|
||||
|((PIOB->PIO_PDSR & (1<<26))>>18)\
|
||||
|((PIOA->PIO_PDSR & (3<<14))>>5)\
|
||||
|((PIOD->PIO_PDSR & (15<<0))<<11)\
|
||||
|((PIOD->PIO_PDSR & (1<<6))<<9)\
|
||||
)
|
||||
#define read_8() (read_16() & 0xFF)
|
||||
#define setWriteDir() {\
|
||||
PIOA->PIO_OER = AMASK; PIOA->PIO_PER = AMASK; \
|
||||
PIOB->PIO_OER = BMASK; PIOB->PIO_PER = BMASK; \
|
||||
PIOC->PIO_OER = CMASK; PIOC->PIO_PER = CMASK; \
|
||||
PIOD->PIO_OER = DMASK; PIOD->PIO_PER = DMASK; \
|
||||
}
|
||||
#define setReadDir() { \
|
||||
PMC->PMC_PCER0 = (1 << ID_PIOA)|(1 << ID_PIOB)|(1 << ID_PIOC)|(1 << ID_PIOD); \
|
||||
PIOA->PIO_ODR = AMASK; \
|
||||
PIOB->PIO_ODR = BMASK; \
|
||||
PIOC->PIO_ODR = CMASK; \
|
||||
PIOD->PIO_ODR = DMASK; \
|
||||
}
|
||||
#define write8(x) { write16(x & 0xFF); }
|
||||
// ILI9486 is slower than ILI9481
|
||||
#define write16(x) { write_16(x); WR_ACTIVE; WR_ACTIVE; WR_STROBE; }
|
||||
#define READ_16(dst) { RD_STROBE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; dst = read_16(); RD_IDLE; RD_IDLE; RD_IDLE; }
|
||||
#define READ_8(dst) { READ_16(dst); dst &= 0xFF; }
|
||||
|
||||
// Shield Control macros.
|
||||
#define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin))
|
||||
#define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin))
|
||||
#define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin))
|
||||
|
||||
#elif defined(__SAM3X8E__) && defined(USE_MEGA_8BIT_SHIELD) //regular CTE shield on DUE
|
||||
#warning USE_MEGA_8BIT_SHIELD for peloxp
|
||||
// configure macros for the control pins
|
||||
#define RD_PORT PIOA
|
||||
#define RD_PIN 20 //D43
|
||||
#define WR_PORT PIOC
|
||||
#define WR_PIN 7 //D39
|
||||
#define CD_PORT PIOC
|
||||
#define CD_PIN 6 //D38
|
||||
#define CS_PORT PIOC
|
||||
#define CS_PIN 8 //D40
|
||||
#define RESET_PORT PIOC
|
||||
#define RESET_PIN 9 //D41
|
||||
// configure macros for data bus
|
||||
//
|
||||
#define AMASK ((3<<14)) //PA14-PA15 D23-D24
|
||||
#define BMASK (1<<26) //PB26 D22
|
||||
#define DMASK ((15<<0)|(1<<6)) //PD0-PD3, PD6 D25-D28,D29
|
||||
|
||||
#define write_8(x) { PIOA->PIO_CODR = AMASK; PIOB->PIO_CODR = BMASK; PIOD->PIO_CODR = DMASK; \
|
||||
PIOB->PIO_SODR = (((x)&(1<<0))<<26); \
|
||||
PIOA->PIO_SODR = (((x)&(3<<1))<<13); \
|
||||
PIOD->PIO_SODR = (((x)&(15<<3))>>3); \
|
||||
PIOD->PIO_SODR = (((x)&(1<<7))>>1); \
|
||||
}
|
||||
|
||||
#define read_8() ( 0\
|
||||
|((PIOB->PIO_PDSR & (1<<26))>>26)\
|
||||
|((PIOA->PIO_PDSR & (3<<14))>>13)\
|
||||
|((PIOD->PIO_PDSR & (15<<0))<<3)\
|
||||
|((PIOD->PIO_PDSR & (1<<6))<<1)\
|
||||
)
|
||||
|
||||
#define setWriteDir() {\
|
||||
PIOA->PIO_OER = AMASK; PIOA->PIO_PER = AMASK; \
|
||||
PIOB->PIO_OER = BMASK; PIOB->PIO_PER = BMASK; \
|
||||
PIOD->PIO_OER = DMASK; PIOD->PIO_PER = DMASK; \
|
||||
}
|
||||
#define setReadDir() { \
|
||||
PMC->PMC_PCER0 = (1 << ID_PIOA)|(1 << ID_PIOB)|(1 << ID_PIOC)|(1 << ID_PIOD); \
|
||||
PIOA->PIO_ODR = AMASK; \
|
||||
PIOB->PIO_ODR = BMASK; \
|
||||
PIOD->PIO_ODR = DMASK; \
|
||||
}
|
||||
|
||||
// ILI9486 is slower than ILI9481
|
||||
#define write8(x) { write_8(x); WR_ACTIVE; WR_ACTIVE; WR_STROBE; WR_IDLE; WR_IDLE; }
|
||||
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
|
||||
#define READ_8(dst) { RD_STROBE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; dst = read_8(); RD_IDLE; RD_IDLE; RD_IDLE; }
|
||||
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
|
||||
|
||||
// Shield Control macros.
|
||||
#define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin))
|
||||
#define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin))
|
||||
#define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin))
|
||||
|
||||
#elif defined(__MK20DX256__) && defined(USE_BOBCACHELOT_TEENSY) // special for BOBCACHEALOT_TEENSY
|
||||
#warning special for BOBCACHEALOT_TEENSY
|
||||
#define RD_PORT GPIOD
|
||||
#define RD_PIN 1
|
||||
#define WR_PORT GPIOC
|
||||
#define WR_PIN 0
|
||||
#define CD_PORT GPIOB
|
||||
#define CD_PIN 0
|
||||
#define CS_PORT GPIOB
|
||||
#define CS_PIN 1
|
||||
#define RESET_PORT GPIOB
|
||||
#define RESET_PIN 3
|
||||
|
||||
// configure macros for the data pins
|
||||
#define CMASK ((1<<3))
|
||||
#define DMASK ((1<<0)|(1<<2)|(1<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7))
|
||||
|
||||
#define write_8(d) { \
|
||||
GPIOC_PCOR = CMASK; GPIOD_PCOR = DMASK; \
|
||||
GPIOC_PSOR = (((d) & (1<<1)) << 2); \
|
||||
GPIOD_PSOR = (d) & DMASK; \
|
||||
}
|
||||
#define read_8() ( (GPIOD_PDIR & DMASK) | (GPIOC_PDIR & (1<<3)) >> 2 )
|
||||
#define setWriteDir() {GPIOC_PDDR |= CMASK;GPIOD_PDDR |= DMASK; }
|
||||
#define setReadDir() {GPIOC_PDDR &= ~CMASK;GPIOD_PDDR &= ~DMASK; }
|
||||
|
||||
#define write8(x) { write_8(x); WR_STROBE; }
|
||||
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
|
||||
#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
|
||||
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
|
||||
|
||||
#define PASTE(x, y) x ## y
|
||||
|
||||
#define PIN_LOW(port, pin) PASTE(port, _PCOR) = (1<<(pin))
|
||||
#define PIN_HIGH(port, pin) PASTE(port, _PSOR) = (1<<(pin))
|
||||
#define PIN_OUTPUT(port, pin) PASTE(port, _PDDR) |= (1<<(pin))
|
||||
|
||||
#elif defined(__MK20DX128__) && defined(USE_FRDM_K20) // Uno Shield on FRDM-K20
|
||||
#warning Uno Shield on FRDM-K20
|
||||
#define RD_PORT GPIOC
|
||||
#define RD_PIN 0
|
||||
#define WR_PORT GPIOC
|
||||
#define WR_PIN 1
|
||||
#define CD_PORT GPIOD
|
||||
#define CD_PIN 6
|
||||
#define CS_PORT GPIOD
|
||||
#define CS_PIN 5
|
||||
#define RESET_PORT GPIOB
|
||||
#define RESET_PIN 1
|
||||
|
||||
// configure macros for the data pins
|
||||
#define AMASK ((1<<12)|(1<<5)|(1<<2)|(1<<1))
|
||||
#define CMASK ((1<<8)|(1<<4)|(1<<3))
|
||||
#define DMASK ((1<<4))
|
||||
#define write_8(d) { \
|
||||
GPIOA_PCOR = AMASK; GPIOC_PCOR = CMASK; GPIOD_PCOR = DMASK; \
|
||||
GPIOA_PSOR = (((d) & (1<<0)) << 12) \
|
||||
| (((d) & (1<<1)) << 1) \
|
||||
| (((d) & (1<<2)) << 3) \
|
||||
| (((d) & (1<<5)) >> 4); \
|
||||
GPIOC_PSOR = (((d) & (1<<4)) << 4) \
|
||||
| (((d) & (3<<6)) >> 3); \
|
||||
GPIOD_PSOR = (((d) & (1<<3)) << 1); \
|
||||
}
|
||||
#define read_8() ( (((GPIOA_PDIR & (1<<5)) >> 3) \
|
||||
| ((GPIOA_PDIR & (1<<1)) << 4) \
|
||||
| ((GPIOA_PDIR & (1<<12)) >> 12) \
|
||||
| ((GPIOA_PDIR & (1<<2)) >> 1) \
|
||||
| ((GPIOC_PDIR & (1<<8)) >> 4) \
|
||||
| ((GPIOC_PDIR & (3<<3)) << 3) \
|
||||
| ((GPIOD_PDIR & (1<<4)) >> 1)))
|
||||
#define setWriteDir() {GPIOA_PDDR |= AMASK;GPIOC_PDDR |= CMASK;GPIOD_PDDR |= DMASK; }
|
||||
#define setReadDir() {GPIOA_PDDR &= ~AMASK;GPIOC_PDDR &= ~CMASK;GPIOD_PDDR &= ~DMASK; }
|
||||
|
||||
#define write8(x) { write_8(x); WR_ACTIVE; WR_ACTIVE; WR_STROBE; }
|
||||
#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
|
||||
#define READ_8(dst) { RD_STROBE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; dst = read_8(); RD_IDLE; }
|
||||
#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
|
||||
|
||||
#define PASTE(x, y) x ## y
|
||||
|
||||
#define PIN_LOW(port, pin) PASTE(port, _PCOR) = (1<<(pin))
|
||||
#define PIN_HIGH(port, pin) PASTE(port, _PSOR) = (1<<(pin))
|
||||
#define PIN_OUTPUT(port, pin) PASTE(port, _PDDR) |= (1<<(pin))
|
||||
|
||||
#else
|
||||
#define USE_SPECIAL_FAIL
|
||||
#endif
|
||||
545
utility/pin_shield_1.h
Normal file
545
utility/pin_shield_1.h
Normal file
@@ -0,0 +1,545 @@
|
||||
#ifndef PIN_SHIELD_1_H_
|
||||
#define PIN_SHIELD_1_H_
|
||||
|
||||
// just provide macros for the Arduino pins
|
||||
// i.e. PIN_LOW(), PIN_HIGH(), PIN_OUTPUT(), PIN_INPUT(), PIN_READ()
|
||||
|
||||
#define LPC810 810
|
||||
#define LPC812 812
|
||||
#define LPC1343 1343
|
||||
#define LPC1768 1768
|
||||
#define LPC2103 2103
|
||||
#define LPC2148 2148
|
||||
#warning Using pin_SHIELD_1.h
|
||||
|
||||
#if 0
|
||||
|
||||
#elif defined(NUCLEO) || defined(TARGET_NUCLEO_F072RB) || defined(TARGET_NUCLEO_F401RE) || defined(TARGET_NUCLEO_F411RE) || defined(TARGET_NUCLEO_F103RB)
|
||||
#define PIN_MODE2(reg, pin, mode) reg=(reg&~(0x3<<((pin)<<1)))|(mode<<((pin)<<1))
|
||||
#if __MBED__
|
||||
#warning MBED knows everything
|
||||
#elif defined(STM32F072xB)
|
||||
#include <STM32F0XX.h>
|
||||
#elif defined(STM32F103xB)
|
||||
#if defined(__CC_ARM)
|
||||
#include <STM32F10X.h>
|
||||
#else
|
||||
#include <STM32F1XX.h>
|
||||
#endif
|
||||
#elif defined(STM32L476xx)
|
||||
#include <STM32L4XX.h>
|
||||
#elif defined(STM32F401xE) || defined(STM32F411xE)
|
||||
#include <STM32F4XX.h>
|
||||
#endif
|
||||
#define D0_PORT GPIOA
|
||||
#define D0_PIN 3
|
||||
#define D1_PORT GPIOA
|
||||
#define D1_PIN 2
|
||||
#define D2_PORT GPIOA
|
||||
#define D2_PIN 10
|
||||
#define D3_PORT GPIOB
|
||||
#define D3_PIN 3
|
||||
#define D4_PORT GPIOB
|
||||
#define D4_PIN 5
|
||||
#define D5_PORT GPIOB
|
||||
#define D5_PIN 4
|
||||
#define D6_PORT GPIOB
|
||||
#define D6_PIN 10
|
||||
#define D7_PORT GPIOA
|
||||
#define D7_PIN 8
|
||||
#define D8_PORT GPIOA
|
||||
#define D8_PIN 9
|
||||
#define D9_PORT GPIOC
|
||||
#define D9_PIN 7
|
||||
#define D10_PORT GPIOB
|
||||
#define D10_PIN 6
|
||||
#define D11_PORT GPIOA
|
||||
#define D11_PIN 7
|
||||
#define D12_PORT GPIOA
|
||||
#define D12_PIN 6
|
||||
#define D13_PORT GPIOA
|
||||
#define D13_PIN 5
|
||||
#define A0_PORT GPIOA
|
||||
#define A0_PIN 0
|
||||
#define A1_PORT GPIOA
|
||||
#define A1_PIN 1
|
||||
#define A2_PORT GPIOA
|
||||
#define A2_PIN 4
|
||||
#define A3_PORT GPIOB
|
||||
#define A3_PIN 0
|
||||
#define A4_PORT GPIOC
|
||||
#define A4_PIN 1
|
||||
#define A5_PORT GPIOC
|
||||
#define A5_PIN 0
|
||||
// Shield Control macros
|
||||
#define PIN_LOW(port, pin) (port)->BSRR = (1<<((pin)+16))
|
||||
#define PIN_HIGH(port, pin) (port)->BSRR = (1<<(pin))
|
||||
//#define PIN_LOW(port, pin) (port)->ODR &= ~(1<<(pin))
|
||||
//#define PIN_HIGH(port, pin) (port)->ODR |= (1<<(pin))
|
||||
#define PIN_READ(port, pin) (port)->IDR & (1<<(pin))
|
||||
#if defined(STM32F103xB)
|
||||
#warning STM32F103xB ******************************
|
||||
#define PIN_MODE4(reg, pin, mode) reg=(reg&~(0xF<<((pin)<<2)))|(mode<<((pin)<<2))
|
||||
#define PIN_OUTPUT(port, pin) PIN_MODE4((port)->CRL, pin, 0x3) //50MHz push-pull only 0-7
|
||||
#define PIN_INPUT(port, pin) PIN_MODE4((port)->CRL, pin, 0x4) //digital input
|
||||
#else
|
||||
#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
|
||||
#define PIN_INPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x0) //.kbv check this
|
||||
#endif
|
||||
|
||||
#elif __TARGET_PROCESSOR == LPC1768
|
||||
#include <LPC17xx.h>
|
||||
// configure macros for the control pins
|
||||
#define D0_PORT LPC_GPIO0
|
||||
#define D0_PIN 3
|
||||
#define D1_PORT LPC_GPIO0
|
||||
#define D1_PIN 2
|
||||
#define D2_PORT LPC_GPIO0
|
||||
#define D2_PIN 24 //p16
|
||||
#define D3_PORT LPC_GPIO0
|
||||
#define D3_PIN 23 //p15
|
||||
#define D4_PORT LPC_GPIO0
|
||||
#define D4_PIN 16 //p14
|
||||
#define D5_PORT LPC_GPIO0
|
||||
#define D5_PIN 15 //p13
|
||||
#define D6_PORT LPC_GPIO0
|
||||
#define D6_PIN 17 //p12
|
||||
#define D7_PORT LPC_GPIO0
|
||||
#define D7_PIN 18 //p11
|
||||
#define D8_PORT LPC_GPIO0
|
||||
#define D8_PIN 1 //p10
|
||||
#define D9_PORT LPC_GPIO0
|
||||
#define D9_PIN 0 //p9
|
||||
#define D10_PORT LPC_GPIO0
|
||||
#define D10_PIN 6 //p8
|
||||
#define D11_PORT LPC_GPIO0
|
||||
#define D11_PIN 9 //p5
|
||||
#define D12_PORT LPC_GPIO0
|
||||
#define D12_PIN 8 //p6 miso
|
||||
#define D13_PORT LPC_GPIO0
|
||||
#define D13_PIN 7 //p7
|
||||
#define A0_PORT LPC_GPIO0
|
||||
#define A0_PIN 25 //p17
|
||||
#define A1_PORT LPC_GPIO0
|
||||
#define A1_PIN 26 //p18
|
||||
#define A2_PORT LPC_GPIO1
|
||||
#define A2_PIN 30 //p19
|
||||
#define A3_PORT LPC_GPIO1
|
||||
#define A3_PIN 31 //p20
|
||||
#define A4_PORT LPC_GPIO0
|
||||
#define A4_PIN 10 //p28
|
||||
#define A5_PORT LPC_GP100
|
||||
#define A5_PIN 11 //p27
|
||||
// Shield Control macros
|
||||
#define PIN_LOW(port, pin) (port)->FIOCLR = (1u<<(pin))
|
||||
#define PIN_HIGH(port, pin) (port)->FIOSET = (1u<<(pin))
|
||||
#define PIN_OUTPUT(port, pin) (port)->FIODIR |= (1u<<(pin))
|
||||
#define PIN_INPUT(port, pin) (port)->FIODIR &= ~(1u<<(pin))
|
||||
#define PIN_READ(port, pin) (port)->FIOPIN & (1u<<(pin))
|
||||
|
||||
#elif defined(MK20D7) && defined(TEENSY)
|
||||
#include <MK20D5.h>
|
||||
#define D0_PORT PTB
|
||||
#define D0_PIN 16
|
||||
#define D1_PORT PTB
|
||||
#define D1_PIN 17
|
||||
#define D2_PORT PTD
|
||||
#define D2_PIN 0
|
||||
#define D3_PORT PTA
|
||||
#define D3_PIN 12
|
||||
#define D4_PORT PTA
|
||||
#define D4_PIN 13
|
||||
#define D5_PORT PTD
|
||||
#define D5_PIN 7
|
||||
#define D6_PORT PTD
|
||||
#define D6_PIN 4
|
||||
#define D7_PORT PTD
|
||||
#define D7_PIN 2
|
||||
#define D8_PORT PTD
|
||||
#define D8_PIN 3
|
||||
#define D9_PORT PTC
|
||||
#define D9_PIN 3
|
||||
#define D10_PORT PTC
|
||||
#define D10_PIN 4
|
||||
#define D11_PORT PTC
|
||||
#define D11_PIN 6
|
||||
#define D12_PORT PTC
|
||||
#define D12_PIN 7
|
||||
#define D13_PORT PTC
|
||||
#define D13_PIN 5
|
||||
#define A0_PORT PTD
|
||||
#define A0_PIN 1
|
||||
#define A1_PORT PTC
|
||||
#define A1_PIN 0
|
||||
#define A2_PORT PTB
|
||||
#define A2_PIN 0
|
||||
#define A3_PORT PTB
|
||||
#define A3_PIN 1
|
||||
#define A4_PORT PTB
|
||||
#define A4_PIN 3
|
||||
#define A5_PORT PTB
|
||||
#define A5_PIN 2
|
||||
// Shield Control macros. Deliberately avoid the IOSET registers
|
||||
#define PIN_LOW(port, pin) (port)->PCOR = (1<<(pin))
|
||||
#define PIN_HIGH(port, pin) (port)->PSOR = (1<<(pin))
|
||||
//#define PIN_LOW(port, pin) (port)->PDOR &= ~(1<<(pin))
|
||||
//#define PIN_HIGH(port, pin) (port)->PDOR |= (1<<(pin))
|
||||
#define PIN_OUTPUT(port, pin) (port)->PDDR |= (1<<(pin))
|
||||
#define PIN_INPUT(port, pin) (port)->PDDR &= ~(1u<<(pin))
|
||||
#define PIN_READ(port, pin) (port)->PDIR & (1u<<(pin))
|
||||
|
||||
|
||||
#elif defined(MKL25Z4) || defined(TARGET_KL25Z)
|
||||
#include <MKL25Z4.h>
|
||||
#define D0_PORT PTA
|
||||
#define D0_PIN 1
|
||||
#define D1_PORT PTA
|
||||
#define D1_PIN 2
|
||||
#define D2_PORT PTD
|
||||
#define D2_PIN 4
|
||||
#define D3_PORT PTA
|
||||
#define D3_PIN 12
|
||||
#define D4_PORT PTA
|
||||
#define D4_PIN 4
|
||||
#define D5_PORT PTA
|
||||
#define D5_PIN 5
|
||||
#define D6_PORT PTC
|
||||
#define D6_PIN 8
|
||||
#define D7_PORT PTC
|
||||
#define D7_PIN 9
|
||||
#define D8_PORT PTA
|
||||
#define D8_PIN 13
|
||||
#define D9_PORT PTD
|
||||
#define D9_PIN 5
|
||||
#define D10_PORT PTD
|
||||
#define D10_PIN 0
|
||||
#define D11_PORT PTD
|
||||
#define D11_PIN 2
|
||||
#define D12_PORT PTD
|
||||
#define D12_PIN 3
|
||||
#define D13_PORT PTD
|
||||
#define D13_PIN 1
|
||||
#define A0_PORT PTB
|
||||
#define A0_PIN 0
|
||||
#define A1_PORT PTB
|
||||
#define A1_PIN 1
|
||||
#define A2_PORT PTB
|
||||
#define A2_PIN 2
|
||||
#define A3_PORT PTB
|
||||
#define A3_PIN 3
|
||||
#define A4_PORT PTC
|
||||
#define A4_PIN 2
|
||||
#define A5_PORT PTC
|
||||
#define A5_PIN 1
|
||||
// Shield Control macros. Deliberately avoid the IOSET registers
|
||||
#define PIN_LOW(port, pin) (port)->PCOR = (1<<(pin))
|
||||
#define PIN_HIGH(port, pin) (port)->PSOR = (1<<(pin))
|
||||
//#define PIN_LOW(port, pin) (port)->PDOR &= ~(1<<(pin))
|
||||
//#define PIN_HIGH(port, pin) (port)->PDOR |= (1<<(pin))
|
||||
#define PIN_OUTPUT(port, pin) (port)->PDDR |= (1<<(pin))
|
||||
#define PIN_INPUT(port, pin) (port)->PDDR &= ~(1u<<(pin))
|
||||
#define PIN_READ(port, pin) (port)->PDIR & (1u<<(pin))
|
||||
|
||||
#elif defined(MKL05Z4)
|
||||
#include <MKL05Z4.h>
|
||||
#define D0_PORT PTB
|
||||
#define D0_PIN 2
|
||||
#define D1_PORT PTB
|
||||
#define D1_PIN 1
|
||||
#define D2_PORT PTA
|
||||
#define D2_PIN 11
|
||||
#define D3_PORT PTB
|
||||
#define D3_PIN 5
|
||||
#define D4_PORT PTA
|
||||
#define D4_PIN 10
|
||||
#define D5_PORT PTA
|
||||
#define D5_PIN 12
|
||||
#define D6_PORT PTB
|
||||
#define D6_PIN 6
|
||||
#define D7_PORT PTB
|
||||
#define D7_PIN 7
|
||||
#define D8_PORT PTB
|
||||
#define D8_PIN 13
|
||||
#define D9_PORT PTB
|
||||
#define D9_PIN 5
|
||||
#define D10_PORT PTA
|
||||
#define D10_PIN 0
|
||||
#define D11_PORT PTA
|
||||
#define D11_PIN 2
|
||||
#define D12_PORT PTA
|
||||
#define D12_PIN 3
|
||||
#define D13_PORT PTB
|
||||
#define D13_PIN 1
|
||||
#define A0_PORT PTB
|
||||
#define A0_PIN 8
|
||||
#define A1_PORT PTB
|
||||
#define A1_PIN 9
|
||||
#define A2_PORT PTA
|
||||
#define A2_PIN 8
|
||||
#define A3_PORT PTA
|
||||
#define A3_PIN 0
|
||||
#define A4_PORT PTA
|
||||
#define A4_PIN 9
|
||||
#define A5_PORT PTB
|
||||
#define A5_PIN 13
|
||||
// Shield Control macros
|
||||
//#define PIN_LOW(port, pin) (port)->PCOR = (1<<(pin))
|
||||
//#define PIN_HIGH(port, pin) (port)->PSOR = (1<<(pin))
|
||||
#define PIN_LOW(port, pin) (port)->PDOR &= ~(1<<(pin))
|
||||
#define PIN_HIGH(port, pin) (port)->PDOR |= (1<<(pin))
|
||||
#define PIN_OUTPUT(port, pin) (port)->PDDR |= (1<<(pin))
|
||||
#define PIN_INPUT(port, pin) (port)->PDDR &= ~(1u<<(pin))
|
||||
#define PIN_READ(port, pin) (port)->PDIR & (1u<<(pin))
|
||||
|
||||
#elif defined(MK20D5) || defined(TARGET_K20D50M)
|
||||
#include <MK20D5.h>
|
||||
#define D0_PORT PTE
|
||||
#define D0_PIN 1
|
||||
#define D1_PORT PTE
|
||||
#define D1_PIN 0
|
||||
#define D2_PORT PTA
|
||||
#define D2_PIN 5
|
||||
#define D3_PORT PTD
|
||||
#define D3_PIN 4
|
||||
#define D4_PORT PTC
|
||||
#define D4_PIN 8
|
||||
#define D5_PORT PTA
|
||||
#define D5_PIN 1
|
||||
#define D6_PORT PTC
|
||||
#define D6_PIN 3
|
||||
#define D7_PORT PTC
|
||||
#define D7_PIN 4
|
||||
#define D8_PORT PTA
|
||||
#define D8_PIN 13
|
||||
#define D9_PORT PTA
|
||||
#define D9_PIN 5
|
||||
#define D10_PORT PTC
|
||||
#define D10_PIN 0
|
||||
#define D11_PORT PTD
|
||||
#define D11_PIN 2
|
||||
#define D12_PORT PTD
|
||||
#define D12_PIN 3
|
||||
#define D13_PORT PTD
|
||||
#define D13_PIN 1
|
||||
#define A0_PORT PTC
|
||||
#define A0_PIN 0
|
||||
#define A1_PORT PTC
|
||||
#define A1_PIN 1
|
||||
#define A2_PORT PTD
|
||||
#define A2_PIN 6
|
||||
#define A3_PORT PTD
|
||||
#define A3_PIN 5
|
||||
#define A4_PORT PTB
|
||||
#define A4_PIN 1
|
||||
#define A5_PORT PTB
|
||||
#define A5_PIN 0
|
||||
// Shield Control macros. Deliberately avoid the IOSET registers
|
||||
#define PIN_LOW(port, pin) (port)->PCOR = (1<<(pin))
|
||||
#define PIN_HIGH(port, pin) (port)->PSOR = (1<<(pin))
|
||||
//#define PIN_LOW(port, pin) (port)->PDOR &= ~(1<<(pin))
|
||||
//#define PIN_HIGH(port, pin) (port)->PDOR |= (1<<(pin))
|
||||
#define PIN_OUTPUT(port, pin) (port)->PDDR |= (1<<(pin))
|
||||
#define PIN_INPUT(port, pin) (port)->PDDR &= ~(1u<<(pin))
|
||||
#define PIN_READ(port, pin) (port)->PDIR & (1u<<(pin))
|
||||
|
||||
|
||||
#elif defined(ZERO)
|
||||
#include <samd21.h>
|
||||
// configure macros for the data pins
|
||||
#if defined(D21_XPRO)
|
||||
#define D0_PORT PORT->Group[1]
|
||||
#define D0_PIN 9
|
||||
#define D1_PORT PORT->Group[1]
|
||||
#define D1_PIN 8
|
||||
#define D2_PORT PORT->Group[1]
|
||||
#define D2_PIN 14
|
||||
#define D3_PORT PORT->Group[1]
|
||||
#define D3_PIN 2
|
||||
#define D4_PORT PORT->Group[1]
|
||||
#define D4_PIN 5
|
||||
#define D5_PORT PORT->Group[0]
|
||||
#define D5_PIN 21
|
||||
#define D6_PORT PORT->Group[1]
|
||||
#define D6_PIN 15
|
||||
#define D7_PORT PORT->Group[0]
|
||||
#define D7_PIN 17
|
||||
#define D8_PORT PORT->Group[1]
|
||||
#define D8_PIN 6
|
||||
#define D9_PORT PORT->Group[1]
|
||||
#define D9_PIN 7
|
||||
#define D10_PORT PORT->Group[0]
|
||||
#define D10_PIN 5
|
||||
#define D11_PORT PORT->Group[0]
|
||||
#define D11_PIN 6
|
||||
#define D12_PORT PORT->Group[0]
|
||||
#define D12_PIN 4
|
||||
#define D13_PORT PORT->Group[0]
|
||||
#define D13_PIN 7
|
||||
#define A0_PORT PORT->Group[1]
|
||||
#define A0_PIN 0
|
||||
#define A1_PORT PORT->Group[1]
|
||||
#define A1_PIN 1
|
||||
#define A2_PORT PORT->Group[0]
|
||||
#define A2_PIN 10
|
||||
#define A3_PORT PORT->Group[0]
|
||||
#define A3_PIN 11
|
||||
#define A4_PORT PORT->Group[0]
|
||||
#define A4_PIN 8
|
||||
#define A5_PORT PORT->Group[0]
|
||||
#define A5_PIN 9
|
||||
#elif defined(M0_PRO)
|
||||
#define D0_PORT PORT->Group[0]
|
||||
#define D0_PIN 11
|
||||
#define D1_PORT PORT->Group[0]
|
||||
#define D1_PIN 10
|
||||
#define D2_PORT PORT->Group[0]
|
||||
#define D2_PIN 8
|
||||
#define D3_PORT PORT->Group[0]
|
||||
#define D3_PIN 9
|
||||
#define D4_PORT PORT->Group[0]
|
||||
#define D4_PIN 14
|
||||
#define D5_PORT PORT->Group[0]
|
||||
#define D5_PIN 15
|
||||
#define D6_PORT PORT->Group[0]
|
||||
#define D6_PIN 20
|
||||
#define D7_PORT PORT->Group[0]
|
||||
#define D7_PIN 21
|
||||
#define D8_PORT PORT->Group[0]
|
||||
#define D8_PIN 6
|
||||
#define D9_PORT PORT->Group[0]
|
||||
#define D9_PIN 7
|
||||
#define D10_PORT PORT->Group[0]
|
||||
#define D10_PIN 18
|
||||
#define D11_PORT PORT->Group[0]
|
||||
#define D11_PIN 16
|
||||
#define D12_PORT PORT->Group[0]
|
||||
#define D12_PIN 19
|
||||
#define D13_PORT PORT->Group[0]
|
||||
#define D13_PIN 17
|
||||
#define A0_PORT PORT->Group[0]
|
||||
#define A0_PIN 2
|
||||
#define A1_PORT PORT->Group[1]
|
||||
#define A1_PIN 8
|
||||
#define A2_PORT PORT->Group[1]
|
||||
#define A2_PIN 9
|
||||
#define A3_PORT PORT->Group[0]
|
||||
#define A3_PIN 4
|
||||
#define A4_PORT PORT->Group[0]
|
||||
#define A4_PIN 5
|
||||
#define A5_PORT PORT->Group[1]
|
||||
#define A5_PIN 2
|
||||
|
||||
#endif
|
||||
// Shield Control macros.
|
||||
#define PIN_LOW(port, pin) (port).OUTCLR.reg = (1<<(pin))
|
||||
#define PIN_HIGH(port, pin) (port).OUTSET.reg = (1<<(pin))
|
||||
#define PIN_OUTPUT(port, pin) (port).DIR.reg |= (1<<(pin))
|
||||
#define PIN_INPUT(port, pin) (port).DIR.reg &= ~(1u<<(pin))
|
||||
#define PIN_READ(port, pin) (port).IN.reg & (1u<<(pin))
|
||||
|
||||
|
||||
#elif defined(__AVR_ATxmegaA4U__)
|
||||
#include <avr/io.h>
|
||||
// PD6, PD7 is used for USB. I could have used PORTA for bus, PORTC for MSPI, SPI and remap
|
||||
#define D0_PORT PORTE
|
||||
#define D0_PIN 2
|
||||
#define D1_PORT PORTE
|
||||
#define D1_PIN 3
|
||||
#define D2_PORT PORTC
|
||||
#define D2_PIN 2
|
||||
#define D3_PORT PORTC
|
||||
#define D3_PIN 3
|
||||
#define D4_PORT PORTC
|
||||
#define D4_PIN 4
|
||||
#define D5_PORT PORTC
|
||||
#define D5_PIN 5
|
||||
#define D6_PORT PORTC
|
||||
#define D6_PIN 6
|
||||
#define D7_PORT PORTC
|
||||
#define D7_PIN 7
|
||||
#define D8_PORT PORTC
|
||||
#define D8_PIN 0
|
||||
#define D9_PORT PORTC
|
||||
#define D9_PIN 1
|
||||
#define D10_PORT PORTD
|
||||
#define D10_PIN 0
|
||||
#define D11_PORT PORTD
|
||||
#define D11_PIN 3
|
||||
#define D12_PORT PORTD
|
||||
#define D12_PIN 2
|
||||
#define D13_PORT PORTD
|
||||
#define D13_PIN 1
|
||||
#define A0_PORT PORTB
|
||||
#define A0_PIN 0
|
||||
#define A1_PORT PORTB
|
||||
#define A1_PIN 1
|
||||
#define A2_PORT PORTB
|
||||
#define A2_PIN 2
|
||||
#define A3_PORT PORTB
|
||||
#define A3_PIN 3
|
||||
#define A4_PORT PORTE
|
||||
#define A4_PIN 0
|
||||
#define A5_PORT PORTE
|
||||
#define A5_PIN 1
|
||||
// Shield Control macros.
|
||||
#define PIN_LOW(port, pin) (port).OUTCLR.reg = (1<<(pin))
|
||||
#define PIN_HIGH(port, pin) (port).OUTSET.reg = (1<<(pin))
|
||||
#define PIN_OUTPUT(port, pin) (port).DIR.reg |= (1<<(pin))
|
||||
#define PIN_INPUT(port, pin) (port).DIR.reg &= ~(1u<<(pin))
|
||||
#define PIN_READ(port, pin) (port).IN.reg & (1u<<(pin))
|
||||
|
||||
|
||||
#elif defined(__AVR_ATtiny1634__)
|
||||
#include <avr/io.h>
|
||||
//
|
||||
#define D0_PORT PORTA
|
||||
#define D0_PIN 7
|
||||
#define D1_PORT PORTB
|
||||
#define D1_PIN 0
|
||||
#define D2_PORT PORTA
|
||||
#define D2_PIN 0
|
||||
#define D3_PORT PORTA
|
||||
#define D3_PIN 3
|
||||
#define D4_PORT PORTA
|
||||
#define D4_PIN 4
|
||||
#define D5_PORT PORTB
|
||||
#define D5_PIN 3
|
||||
#define D6_PORT PORTA
|
||||
#define D6_PIN 1
|
||||
#define D7_PORT PORTA
|
||||
#define D7_PIN 0
|
||||
#define D8_PORT PORTA
|
||||
#define D8_PIN 2
|
||||
#define D9_PORT PORTB
|
||||
#define D9_PIN 2
|
||||
#define D10_PORT PORTA
|
||||
#define D10_PIN 6
|
||||
#define D11_PORT PORTB
|
||||
#define D11_PIN 2
|
||||
#define D12_PORT PORTB
|
||||
#define D12_PIN 1
|
||||
#define D13_PORT PORTC
|
||||
#define D13_PIN 1
|
||||
#define A0_PORT PORTB
|
||||
#define A0_PIN 3
|
||||
#define A1_PORT PORTC
|
||||
#define A1_PIN 0
|
||||
#define A2_PORT PORTA
|
||||
#define A2_PIN 5
|
||||
#define A3_PORT PORTB
|
||||
#define A3_PIN 2
|
||||
#define A4_PORT PORTB
|
||||
#define A4_PIN 1
|
||||
#define A5_PORT PORTC
|
||||
#define A5_PIN 1
|
||||
#else
|
||||
#error MCU unselected
|
||||
#endif // MCUs
|
||||
|
||||
#endif //PIN_SHIELD_1_H
|
||||
#if 0
|
||||
#if defined(M0_PRO)
|
||||
#endif
|
||||
#if defined(D21_XPRO)
|
||||
#endif
|
||||
#endif
|
||||
286
utility/pin_shield_8.h
Normal file
286
utility/pin_shield_8.h
Normal file
@@ -0,0 +1,286 @@
|
||||
#ifndef PIN_SHIELD_8_H_
|
||||
#define PIN_SHIELD_8_H_
|
||||
|
||||
// just provide macros for the 8-bit data bus
|
||||
// i.e. write_8(), read_8(), setWriteDir(), setReadDir()
|
||||
|
||||
|
||||
#define LPC810 810
|
||||
#define LPC812 812
|
||||
#define LPC1343 1343
|
||||
#define LPC1768 1768
|
||||
#define LPC2103 2103
|
||||
#define LPC2148 2148
|
||||
#warning Using pin_SHIELD_8.h
|
||||
|
||||
#if 0
|
||||
|
||||
#elif defined(NUCLEO) || defined(TARGET_NUCLEO_F072RB) || defined(TARGET_NUCLEO_F401RE) || defined(TARGET_NUCLEO_F411RE) || defined(TARGET_NUCLEO_F103RB)
|
||||
#if __MBED__
|
||||
#warning MBED knows everything
|
||||
#elif defined(STM32F072xB)
|
||||
#include <STM32F0XX.h>
|
||||
#elif defined(STM32F103xB)
|
||||
#if defined(__CC_ARM)
|
||||
#include <STM32F10X.h>
|
||||
#else
|
||||
#include <STM32F1XX.h>
|
||||
#endif
|
||||
#elif defined(STM32L476xx)
|
||||
#include <STM32L4XX.h>
|
||||
#elif defined(STM32F401xE) || defined(STM32F411xE)
|
||||
#include <STM32F4XX.h>
|
||||
#endif
|
||||
// configure macros for the data pins. -00=10.06, -O1=7.85, -O1t=7.21, -O2=7.87, -O3=7.45, -O3t=7.03
|
||||
#define write_8(d) { \
|
||||
GPIOA->BSRR = 0x0700 << 16; \
|
||||
GPIOB->BSRR = 0x0438 << 16; \
|
||||
GPIOC->BSRR = 0x0080 << 16; \
|
||||
GPIOA->BSRR = (((d) & (1<<0)) << 9) \
|
||||
| (((d) & (1<<2)) << 8) \
|
||||
| (((d) & (1<<7)) << 1); \
|
||||
GPIOB->BSRR = (((d) & (1<<3)) << 0) \
|
||||
| (((d) & (1<<4)) << 1) \
|
||||
| (((d) & (1<<5)) >> 1) \
|
||||
| (((d) & (1<<6)) << 4); \
|
||||
GPIOC->BSRR = (((d) & (1<<1)) << 6); \
|
||||
}
|
||||
#define read_8() ( (((GPIOA->IDR & (1<<9)) >> 9) \
|
||||
| ((GPIOC->IDR & (1<<7)) >> 6) \
|
||||
| ((GPIOA->IDR & (1<<10)) >> 8) \
|
||||
| ((GPIOB->IDR & (1<<3)) >> 0) \
|
||||
| ((GPIOB->IDR & (1<<5)) >> 1) \
|
||||
| ((GPIOB->IDR & (1<<4)) << 1) \
|
||||
| ((GPIOB->IDR & (1<<10)) >> 4) \
|
||||
| ((GPIOA->IDR & (1<<8)) >> 1)))
|
||||
// be wise to clear both MODER bits properly.
|
||||
#if defined(STM32F103xB)
|
||||
#define GROUP_MODE(port, reg, mask, val) {port->reg = (port->reg & ~(mask)) | ((mask)&(val)); }
|
||||
#define GP_OUT(port, reg, mask) GROUP_MODE(port, reg, mask, 0x33333333)
|
||||
#define GP_INP(port, reg, mask) GROUP_MODE(port, reg, mask, 0x44444444)
|
||||
// PA10,PA9,PA8 PB10 PB5,PB4,PB3 PC7
|
||||
#define setWriteDir() {GP_OUT(GPIOA, CRH, 0xFFF); GP_OUT(GPIOB, CRH, 0xF00); GP_OUT(GPIOB, CRL, 0xFFF000); GP_OUT(GPIOC, CRL, 0xF0000000); }
|
||||
#define setReadDir() {GP_INP(GPIOA, CRH, 0xFFF); GP_INP(GPIOB, CRH, 0xF00); GP_INP(GPIOB, CRL, 0xFFF000); GP_INP(GPIOC, CRL, 0xF0000000); }
|
||||
#else
|
||||
#define setWriteDir() { setReadDir(); \
|
||||
GPIOA->MODER |= 0x150000; GPIOB->MODER |= 0x100540; GPIOC->MODER |= 0x4000; }
|
||||
#define setReadDir() { GPIOA->MODER &= ~0x3F0000; GPIOB->MODER &= ~0x300FC0; GPIOC->MODER &= ~0xC000; }
|
||||
#endif
|
||||
|
||||
|
||||
#elif __TARGET_PROCESSOR == LPC1768
|
||||
#include <LPC17xx.h>
|
||||
// configure macros for the data pins
|
||||
#define write_8(d) { \
|
||||
LPC_GPIO0->FIOPIN = (LPC_GPIO0->FIOPIN & ~0x01878003) \
|
||||
| (((d) & (1<<0)) << 1) \
|
||||
| (((d) & (1<<1)) >> 1) \
|
||||
| (((d) & (1<<2)) << 22) \
|
||||
| (((d) & (1<<3)) << 20) \
|
||||
| (((d) & (1<<4)) << 12) \
|
||||
| (((d) & (1<<5)) << 10) \
|
||||
| (((d) & (1<<6)) << 11) \
|
||||
| (((d) & (1<<7)) << 11); \
|
||||
}
|
||||
#define read_8() ( (((LPC_GPIO0->FIOPIN & (1<<1)) >> 1) \
|
||||
| ((LPC_GPIO0->FIOPIN & (1<<0)) << 1) \
|
||||
| ((LPC_GPIO0->FIOPIN & (1<<24)) >> 22) \
|
||||
| ((LPC_GPIO0->FIOPIN & (1<<23)) >> 20) \
|
||||
| ((LPC_GPIO0->FIOPIN & (1<<16)) >> 12) \
|
||||
| ((LPC_GPIO0->FIOPIN & (1<<15)) >> 10) \
|
||||
| ((LPC_GPIO0->FIOPIN & (1<<17)) >> 11) \
|
||||
| ((LPC_GPIO0->FIOPIN & (1<<18)) >> 11)))
|
||||
#define setWriteDir() {LPC_GPIO0->FIODIR |= 0x01878003; }
|
||||
#define setReadDir() {LPC_GPIO0->FIODIR &= ~0x01878003; }
|
||||
|
||||
|
||||
#elif defined(MKL25Z4) || defined(TARGET_KL25Z)
|
||||
#include <MKL25Z4.h>
|
||||
// configure macros for the data pins
|
||||
#if 1
|
||||
#define AMASK ((1<<13)|(1<<12)|(1<<5)|(1<<4))
|
||||
#define CMASK ((1<<9)|(1<<8))
|
||||
#define DMASK ((1<<5)|(1<<4))
|
||||
#define write_8(d) { \
|
||||
PTA->PCOR = AMASK; PTC->PCOR = CMASK; PTD->PCOR = DMASK; \
|
||||
PTA->PSOR = (((d) & (1<<0)) << 13) \
|
||||
| (((d) & (1<<3)) << 9) \
|
||||
| (((d) & (1<<4)) >> 0) \
|
||||
| (((d) & (1<<5)) >> 0); \
|
||||
PTC->PSOR = (((d) & (1<<6)) << 2) \
|
||||
| (((d) & (1<<7)) << 2); \
|
||||
PTD->PSOR = (((d) & (1<<1)) << 4) \
|
||||
| (((d) & (1<<2)) << 2); \
|
||||
}
|
||||
#define read_8() ( (((PTA->PDIR & (1<<13)) >> 13) \
|
||||
| ((PTA->PDIR & (1<<12)) >> 9) \
|
||||
| ((PTA->PDIR & (3<<4)) >> 0) \
|
||||
| ((PTC->PDIR & (3<<8)) >> 2) \
|
||||
| ((PTD->PDIR & (1<<4)) >> 2) \
|
||||
| ((PTD->PDIR & (1<<5)) >> 4)))
|
||||
#define setWriteDir() {PTA->PDDR |= AMASK;PTC->PDDR |= CMASK;PTD->PDDR |= DMASK; }
|
||||
#define setReadDir() {PTA->PDDR &= ~AMASK;PTC->PDDR &= ~CMASK;PTD->PDDR &= ~DMASK; }
|
||||
#else
|
||||
#define write_8(d) { \
|
||||
PTA->PDOR = (PTA->PDOR & ~0x3030) \
|
||||
| (((d) & (1<<0)) << 13) \
|
||||
| (((d) & (1<<3)) << 9) \
|
||||
| (((d) & (3<<4)) << 0); \
|
||||
PTC->PDOR = (PTC->PDOR & ~0x0300) \
|
||||
| (((d) & (3<<6)) << 2); \
|
||||
PTD->PDOR = (PTD->PDOR & ~0x0030) \
|
||||
| (((d) & (1<<1)) << 4) \
|
||||
| (((d) & (1<<2)) << 2); \
|
||||
}
|
||||
#define read_8() ( (((PTA->PDIR & (1<<13)) >> 13) \
|
||||
| ((PTA->PDIR & (1<<12)) >> 9) \
|
||||
| ((PTA->PDIR & (3<<4)) >> 0) \
|
||||
| ((PTC->PDIR & (3<<8)) >> 2) \
|
||||
| ((PTD->PDIR & (1<<4)) >> 2) \
|
||||
| ((PTD->PDIR & (1<<5)) >> 4)))
|
||||
#define setWriteDir() {PTA->PDDR |= 0x3030;PTC->PDDR |= 0x0300;PTD->PDDR |= 0x0030; }
|
||||
#define setReadDir() {PTA->PDDR &= ~0x3030;PTC->PDDR &= ~0x0300;PTD->PDDR &= ~0x0030; }
|
||||
#endif
|
||||
|
||||
#elif defined(MKL05Z4) || defined(TARGET_KL05Z)
|
||||
#include <MKL05Z4.h>
|
||||
// configure macros for the data pins
|
||||
#define write_8(d) { \
|
||||
PTA->PDOR = (PTA->PDOR & ~0x1C00) \
|
||||
| (((d) & (1<<2)) << 9) \
|
||||
| (((d) & (1<<4)) << 6) \
|
||||
| (((d) & (1<<5)) << 7); \
|
||||
PTB->PDOR = (PTB->PDOR & ~0x0CE0) \
|
||||
| (((d) & (3<<0)) << 10) \
|
||||
| (((d) & (1<<3)) << 2) \
|
||||
| (((d) & (3<<6)) << 0); \
|
||||
}
|
||||
#define read_8() ( (((PTA->PDIR & (1<<11)) >> 9) \
|
||||
| ((PTA->PDIR & (1<<10)) >> 6) \
|
||||
| ((PTA->PDIR & (1<<12)) >> 7) \
|
||||
| ((PTB->PDIR & (3<<10)) >> 10) \
|
||||
| ((PTB->PDIR & (1<<5)) >> 2) \
|
||||
| ((PTB->PDIR & (3<<6)) >> 0)))
|
||||
#define setWriteDir() { PTA->PDDR |= 0x1C00; PTB->PDDR |= 0x0CE0; }
|
||||
#define setReadDir() { PTA->PDDR &= ~0x1C00; PTB->PDDR &= ~0x0CE0; }
|
||||
|
||||
|
||||
#elif defined(MK20D7) && defined(TEENSY)
|
||||
#include <MK20D5.h>
|
||||
// configure macros for the data pins
|
||||
#define AMASK ((1<<12)|(1<<13))
|
||||
#define CMASK ((1<<3))
|
||||
#define DMASK ((1<<0)|(1<<2)|(1<<3)|(1<<4)|(1<<7))
|
||||
|
||||
#define write_8(d) { \
|
||||
PTA->PCOR = AMASK; PTC->PCOR = CMASK; PTD->PCOR = DMASK; \
|
||||
PTA->PSOR = (((d) & (1<<3)) << 9) \
|
||||
| (((d) & (1<<4)) << 9); \
|
||||
PTC->PSOR = (((d) & (1<<1)) << 2); \
|
||||
PTD->PSOR = (((d) & (1<<0)) << 3) \
|
||||
| (((d) & (1<<2)) >> 2) \
|
||||
| (((d) & (1<<5)) << 2) \
|
||||
| (((d) & (1<<6)) >> 2) \
|
||||
| (((d) & (1<<7)) >> 5); \
|
||||
}
|
||||
#define read_8() ( (((PTD->PDIR & (1<<3)) >> 3) \
|
||||
| ((PTC->PDIR & (1<<3)) >> 2) \
|
||||
| ((PTD->PDIR & (1<<0)) << 2) \
|
||||
| ((PTA->PDIR & (1<<12)) >> 9) \
|
||||
| ((PTA->PDIR & (1<<13)) >> 9) \
|
||||
| ((PTD->PDIR & (1<<7)) >> 2) \
|
||||
| ((PTD->PDIR & (1<<4)) << 2) \
|
||||
| ((PTD->PDIR & (1<<2)) << 5)))
|
||||
#define setWriteDir() {PTA->PDDR |= AMASK;PTC->PDDR |= CMASK;PTD->PDDR |= DMASK; }
|
||||
#define setReadDir() {PTA->PDDR &= ~AMASK;PTC->PDDR &= ~CMASK;PTD->PDDR &= ~DMASK; }
|
||||
|
||||
#elif defined(MK20D5) || defined(TARGET_K20D50M)
|
||||
#include <MK20D5.h>
|
||||
// configure macros for the data pins
|
||||
#define AMASK ((1<<12)|(1<<5)|(1<<2)|(1<<1))
|
||||
#define CMASK ((1<<8)|(1<<4)|(1<<3))
|
||||
#define DMASK ((1<<4))
|
||||
#define write_8(d) { \
|
||||
PTA->PCOR = AMASK; PTC->PCOR = CMASK; PTD->PCOR = DMASK; \
|
||||
PTA->PSOR = (((d) & (1<<0)) << 12) \
|
||||
| (((d) & (1<<1)) << 1) \
|
||||
| (((d) & (1<<2)) << 3) \
|
||||
| (((d) & (1<<5)) >> 4); \
|
||||
PTC->PSOR = (((d) & (1<<4)) << 4) \
|
||||
| (((d) & (3<<6)) >> 3); \
|
||||
PTD->PSOR = (((d) & (1<<3)) << 1); \
|
||||
}
|
||||
#define read_8() ( (((PTA->PDIR & (1<<5)) >> 3) \
|
||||
| ((PTA->PDIR & (1<<1)) << 4) \
|
||||
| ((PTA->PDIR & (1<<12)) >> 12) \
|
||||
| ((PTA->PDIR & (1<<2)) >> 1) \
|
||||
| ((PTC->PDIR & (1<<8)) >> 4) \
|
||||
| ((PTC->PDIR & (3<<3)) << 3) \
|
||||
| ((PTD->PDIR & (1<<4)) >> 1)))
|
||||
#define setWriteDir() {PTA->PDDR |= AMASK;PTC->PDDR |= CMASK;PTD->PDDR |= DMASK; }
|
||||
#define setReadDir() {PTA->PDDR &= ~AMASK;PTC->PDDR &= ~CMASK;PTD->PDDR &= ~DMASK; }
|
||||
|
||||
#elif defined(ZERO)
|
||||
#include <samd21.h>
|
||||
|
||||
#ifndef PORTA
|
||||
#define PORTA PORT->Group[0]
|
||||
#define PORTB PORT->Group[1]
|
||||
#endif
|
||||
// configure macros for the data pins
|
||||
#if defined(D21_XPRO)
|
||||
#define AMASK 0x00220000
|
||||
#define BMASK 0x0000C0E4
|
||||
#define write_8(d) { \
|
||||
PORTA.OUT.reg = (PORTA.OUT.reg & ~AMASK) \
|
||||
| (((d) & (1<<5)) << 16) \
|
||||
| (((d) & (1<<7)) << 10); \
|
||||
PORTB.OUT.reg = (PORTB.OUT.reg & ~BMASK) \
|
||||
| (((d) & (3<<0)) << 6) \
|
||||
| (((d) & (1<<2)) << 12) \
|
||||
| (((d) & (1<<3)) >> 1) \
|
||||
| (((d) & (1<<4)) << 1) \
|
||||
| (((d) & (1<<6)) << 9); \
|
||||
}
|
||||
#define read_8() ( (((PORTA.IN.reg & (1<<21)) >> 16) \
|
||||
| ((PORTA.IN.reg & (1<<17)) >> 10) \
|
||||
| ((PORTB.IN.reg & (3<<6)) >> 6) \
|
||||
| ((PORTB.IN.reg & (1<<14)) >> 12) \
|
||||
| ((PORTB.IN.reg & (1<<2)) << 1) \
|
||||
| ((PORTB.IN.reg & (1<<5)) >> 1) \
|
||||
| ((PORTB.IN.reg & (1<<15)) >> 9)))
|
||||
#define setWriteDir() { \
|
||||
PORTA.DIRSET.reg = AMASK; \
|
||||
PORTB.DIRSET.reg = BMASK; \
|
||||
PORTA.WRCONFIG.reg = (AMASK>>16) | (0<<22) | (0<<28) | (1<<30) | (1<<31); \
|
||||
PORTB.WRCONFIG.reg = (BMASK & 0xFFFF) | (0<<22) | (0<<28) | (1<<30); \
|
||||
}
|
||||
#define setReadDir() { \
|
||||
PORTA.DIRCLR.reg = AMASK; \
|
||||
PORTB.DIRCLR.reg = BMASK; \
|
||||
PORTA.WRCONFIG.reg = (AMASK>>16) | (1<<17) | (0<<28) | (1<<30) | (1<<31); \
|
||||
PORTB.WRCONFIG.reg = (BMASK & 0xFFFF) | (1<<17) | (0<<28) | (1<<30); \
|
||||
}
|
||||
#else
|
||||
#define DMASK 0x0030C3C0
|
||||
#define write_8(x) {PORTA.OUTCLR.reg = (DMASK); \
|
||||
PORTA.OUTSET.reg = (((x) & 0x0F) << 6) \
|
||||
| (((x) & 0x30) << 10) \
|
||||
| (((x) & 0xC0)<<14); }
|
||||
#define read_8() (((PORTA.IN.reg >> 6) & 0x0F) \
|
||||
| ((PORTA.IN.reg >> 10) & 0x30) \
|
||||
| ((PORTA.IN.reg >> 14) & 0xC0))
|
||||
#define setWriteDir() { PORTA.DIRSET.reg = DMASK; \
|
||||
PORTA.WRCONFIG.reg = (DMASK & 0xFFFF) | (0<<22) | (1<<28) | (1<<30); \
|
||||
PORTA.WRCONFIG.reg = (DMASK>>16) | (0<<22) | (1<<28) | (1<<30) | (1<<31); \
|
||||
}
|
||||
#define setReadDir() { PORTA.DIRCLR.reg = DMASK; \
|
||||
PORTA.WRCONFIG.reg = (DMASK & 0xFFFF) | (1<<17) | (1<<28) | (1<<30); \
|
||||
PORTA.WRCONFIG.reg = (DMASK>>16) | (1<<17) | (1<<28) | (1<<30) | (1<<31); \
|
||||
}
|
||||
#endif
|
||||
#else
|
||||
#error MCU unselected
|
||||
#endif // MCUs
|
||||
|
||||
#endif //PIN_SHIELD_8_H
|
||||
Reference in New Issue
Block a user