From 3ed418a78c21d7b7ea7b376390822a044059cd1b Mon Sep 17 00:00:00 2001 From: prenticedavid Date: Sun, 13 Sep 2020 22:40:36 +0100 Subject: [PATCH] update PIONSCOR STM32. add untested NANO33BLE --- extras/unused/mcufriend_special_2.h | 73 +++++++++++++++++++++++++++-- 1 file changed, 68 insertions(+), 5 deletions(-) diff --git a/extras/unused/mcufriend_special_2.h b/extras/unused/mcufriend_special_2.h index ece28f3..c08edaf 100644 --- a/extras/unused/mcufriend_special_2.h +++ b/extras/unused/mcufriend_special_2.h @@ -818,6 +818,63 @@ break; // ################## for auto-format ######################### #if 0 +//####################################### NANO BLE ############################ +#elif defined(ARDUINO_ARDUINO_NANO33BLE) +#warning regular UNO shield on a Nano BLE + +//LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST | +//BLE pin |P0.23|P1.14|P1.13|P1.15|P1.12|P1.11|P0.27|P0.21| |P0.4|P0.5|P0.30|P0.29|P0.31| + +#define WRITE_DELAY { WR_ACTIVE2; } //M4F @ 60MHz +#define IDLE_DELAY { } +#define READ_DELAY { RD_ACTIVE8; RD_ACTIVE; } + +#define RD_PORT NRF_P0 +#define RD_PIN 4 +#define WR_PORT NRF_P0 +#define WR_PIN 5 +#define CD_PORT NRF_P0 +#define CD_PIN 30 +#define CS_PORT NRF_P0 +#define CS_PIN 29 +#define RESET_PORT NRF_P0 +#define RESET_PIN 31 + +// configure macros for the data pins +#define AMASK ((1<<23)|(1<<27)|(1<<21)) //NRF_P0 +#define BMASK ((1<<14)|(1<<13)|(1<<15)|(1<<12)|(1<<11)) //NRF_P1 + +#define write_8(d) { \ + NRF_P0->OUTCLR = AMASK; NRF_P0->OUTCLR = BMASK; \ + NRF_P0->OUTSET = (((d) & (1 << 0)) << 21) \ + | (((d) & (1 << 1)) << 26) \ + | (((d) & (1 << 7)) << 16); \ + NRF_P0->OUTSET = (((d) & (1 << 2)) << 9) \ + | (((d) & (1 << 3)) << 9) \ + | (((d) & (1 << 4)) << 11) \ + | (((d) & (1 << 5)) << 8) \ + | (((d) & (1 << 6)) << 8); \ + } +#define read_8() ((((NRF_P0->IN & (1<<3)) >> 3) \ + | ((NRF_P0->IN & (1 << 3)) >> 2) \ + | ((NRF_P1->IN & (1 << 0)) << 2) \ + | ((NRF_P1->IN & (1 << 12)) >> 9) \ + | ((NRF_P1->IN & (1 << 13)) >> 9) \ + | ((NRF_P1->IN & (1 << 7)) >> 2) \ + | ((NRF_P1->IN & (1 << 4)) << 2) \ + | ((NRF_P0->IN & (1 << 2)) << 5))) +#define setWriteDir() {NRF_P0->DIRSET = AMASK; NRF_P1->DIRSET = BMASK; } +#define setReadDir() {NRF_P0->DIRCLR = AMASK; NRF_P1->DIRCLR = BMASK; } +#define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; IDLE_DELAY; } +#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } +#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; } //PJ adjusted +#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } +#define GPIO_INIT() {for (int i = 2; i <= 9; i++) pinMode(i, OUTPUT); for (int i = A0; i <= A4; i++) pinMode(i, OUTPUT);} + +#define PIN_LOW(port, pin) (port)->OUTCLR = (1<<(pin)) +#define PIN_HIGH(port, pin) (port)->OUTSET = (1<<(pin)) +#define PIN_OUTPUT(port, pin) (port)->DIR |= (1<<(pin)) + // ################## UNO SPECIAL for Stojanjos ############### #define USE_STOJANOS ... @@ -1451,18 +1508,24 @@ break; #define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; } #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } -// #################################### STM32 PIONSCOR ####################################### +// #################################### STM32 PIONSCOR 13SEP2020 ####################################### #define USE_PIONSCOR_BLUEPILL ... -#elif defined(USE_PIONSCOR_BLUEPILL) && (defined(__STM32F1__) || defined(STM32F103xB)) // MAPLECORE or STM32CORE +#elif defined(USE_PIONSCOR_BLUEPILL) && (defined(__STM32F1__) || defined(ARDUINO_BLUEPILL_F103CB)) // MAPLECORE or STM32CORE +//LCD Pins : | D15| D14| D13| D12| D11| D10| D9| D8| D7| D6| D5| D4| D3| D2| D1| D0| +//BLUE PILL: |PB15|PB14|PB13|PB12|PB11|PB10|PB9|PB8|PB7|PB6|PB5|PB4|PB3|PA15|PB1|PB0| +//LCD Pins : |RD |WR |RS |CS |RST | +//BLUE PILL: |PA0 |PA1 |PA2 |PA3 |PA8 | + #warning SSD1963 on USE_PIONSCOR_BLUEPILL #define USES_16BIT_BUS -#if defined(ARDUINO_NUCLEO_F103C8) //regular CMSIS libraries + +#if defined(__STM32F1__) //weird Maple Core +#define REGS(x) regs->x +#else //regular ST Core #define REGS(x) x #define GPIO_INIT() { RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | RCC_APB2ENR_AFIOEN; \ AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_1;} -#else //weird Maple libraries -#define REGS(x) regs->x #endif #define WRITE_DELAY { }