2017-02-18 21:39:02 +00:00
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#ifndef MCUFRIEND_MBED_H_
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#define MCUFRIEND_MBED_H_
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#include <mbed.h>
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#if defined(USE_SERIAL)
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#include "mcufriend_keil_spi.h"
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#else
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BusOut digitalL(D0, D1, D2, D3, D4, D5, D6, D7);
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BusOut digitalH(D8, D9, D10, D11, D12, D13, NC, NC);
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BusOut analog(A0, A1, A2, A3, A4, A5, NC, NC);
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#include "pin_shield_1.h" //shield pin macros e.g. A2_PORT, PIN_OUTPUT()
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#include "pin_shield_8.h" //macros for write_8(), read_8(), setWriteDir(), ...
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// control pins as used in MCUFRIEND shields
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#define RD_PORT A0_PORT
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#define RD_PIN A0_PIN
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#define WR_PORT A1_PORT
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#define WR_PIN A1_PIN
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#define CD_PORT A2_PORT
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#define CD_PIN A2_PIN
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#define CS_PORT A3_PORT
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#define CS_PIN A3_PIN
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#define RESET_PORT A4_PORT
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#define RESET_PIN A4_PIN
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// general purpose pin macros
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#define RD_ACTIVE PIN_LOW(RD_PORT, RD_PIN)
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#define RD_IDLE PIN_HIGH(RD_PORT, RD_PIN)
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#define RD_OUTPUT PIN_OUTPUT(RD_PORT, RD_PIN)
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#define WR_ACTIVE PIN_LOW(WR_PORT, WR_PIN)
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#define WR_IDLE PIN_HIGH(WR_PORT, WR_PIN)
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#define WR_OUTPUT PIN_OUTPUT(WR_PORT, WR_PIN)
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#define CD_COMMAND PIN_LOW(CD_PORT, CD_PIN)
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#define CD_DATA PIN_HIGH(CD_PORT, CD_PIN)
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#define CD_OUTPUT PIN_OUTPUT(CD_PORT, CD_PIN)
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#define CS_ACTIVE PIN_LOW(CS_PORT, CS_PIN)
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#define CS_IDLE PIN_HIGH(CS_PORT, CS_PIN)
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#define CS_OUTPUT PIN_OUTPUT(CS_PORT, CS_PIN)
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#define RESET_ACTIVE PIN_LOW(RESET_PORT, RESET_PIN)
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#define RESET_IDLE PIN_HIGH(RESET_PORT, RESET_PIN)
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#define RESET_OUTPUT PIN_OUTPUT(RESET_PORT, RESET_PIN)
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#if defined(__MK20DX128__) || defined(___MK20DX256__) // Teensy3.0 || 3.2 96MHz
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#define WRITE_DELAY { WR_ACTIVE; WR_ACTIVE; }
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#define READ_DELAY { RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; }
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#elif defined(__MK64FX512__) || defined(TARGET_M4) // Teensy3.5 120MHz thanks to PeteJohno
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#define WRITE_DELAY { WR_ACTIVE; WR_ACTIVE; WR_ACTIVE; WR_ACTIVE; }
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#define READ_DELAY { RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; }
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#elif defined(__MK66FX1M0__) || defined(TARGET_M4) // Teensy3.6 180MHz untested. delays can possibly be reduced.
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#define WRITE_DELAY { WR_ACTIVE; WR_ACTIVE; WR_ACTIVE; WR_ACTIVE; WR_ACTIVE; WR_ACTIVE; WR_ACTIVE; WR_ACTIVE; }
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#define READ_DELAY { RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; }
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#else
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//#error unspecified delays
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#define WRITE_DELAY
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#define READ_DELAY
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#endif
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// General macros. IOCLR registers are 1 cycle when optimised.
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#define WR_STROBE { WR_ACTIVE; WR_IDLE; } //PWLW=TWRL=50ns
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#define RD_STROBE RD_IDLE, RD_ACTIVE, RD_ACTIVE, RD_ACTIVE //PWLR=TRDL=150ns
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#define write8(d) { write_8(d); WRITE_DELAY; WR_STROBE; } // STROBEs are defined later
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#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
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#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; } // read 250ns after RD_ACTIVE goes low
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#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
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#define CTL_INIT() { RD_OUTPUT; WR_OUTPUT; CD_OUTPUT; CS_OUTPUT; RESET_OUTPUT; }
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2018-06-15 00:00:26 +01:00
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#define WriteCmd(x) { CD_COMMAND; write16(x); CD_DATA; }
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#define WriteData(x) { write16(x); }
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2017-02-18 21:39:02 +00:00
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#endif //!USE_SERIAL
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#endif //MCUFRIEND_KEIL_H_
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